Printed Circuit Design & Fab - March 2008 - (Page 26) OPTICAL INTERCONNECT iNEMI Polymer Waveguide Subgroup Polymer waveguide process technology: Technology based on: Monomer diffusion with clad lamination Technology General Attributes Polymerization induced monomer diffusion self development3 Technologies based on: Ridge Formation with clad backfill Image and Screen develop with print, aqueous, molding etching (wet chemical or RIE), laser direct write Rohm & Haas, IBM Embossing Practitioners Optical InterLinks Gemfire/ OptoFoilFraunhofer Dow Corning Institute, IZM FIGURE 3. Polymer waveguide process technology summary. FIGURE 5. Metallized mirror reflected waveguide image for transmitter and receiver coupling. FIGURE 6. Substrate attached waveguide array alignment. FIGURE 4. Board edge connectivity using MT style ferrules. include a light induced imaging reaction, a total polymerization light fixing for the entire film, and final cure, all using pre-coated dry materials without waveguide side wall contact. Light and molecular diffusion determine the guide walls. Several industrial groups and laboratories (some identified in FIGURE 3) exploring the ridge formation style technique also participated in an iNEMI study on optical backplanes. Over 15 groups participated to develop a polymer waveguide technology attribute table. Figure 3 shows the header for the resulting attribute table, listing the two polymer technique class types, with representatives from each subgroup. Both ridge and diffusion technologies have the capability to create self supporting waveguide films that can be micro-machined to provide fully connectable configurations ready for installation. The process techniques can also create waveguide films directly on the final application substrate. A number of unique performance and waveguide configurations can be obtained by the use of the diffusion or ridge guide forming processes. Practical link configurations for optoelectronic substrate interconnectivity involves connectivity options for parallel and functional links. These critical system building blocks used for practical applications are described below, identifying and elaborating on key system attributes. Self-supporting waveguide films are used as the starting point. The basic features demonstrated confirm that practical connectivity is achievable. Optical Interconnects and Connectivity Issues In the following examples the coupling capabilities are demonstrated by the prototype products shown. Critical connectivity issues for practical applications of each are noted. Type One uses substrate edge ferrules with similarly precise aligned waveguides and butt coupling interfaces. Butt coupling (surfaces cut perpendicular to waveguide or fiber axis) can be coupled to fiber arrays or to waveguide arrays held in 26 similar ferrules. FIGURE 4 shows board edge MT ferrules connecting and aligning 12 waveguides to 12 optical fibers. Critical connectivity issues include the need to prevent loss producing micro-bends at the connector interface where the film leaves the board edge into the modified MT ferrule. It is necessary to optimize performance to match fiber and waveguide allowed propagating angles (referred to as numerical aperture, or NA, defined as the sine of the half angle of the radiated Gaussian light pattern at the 5% intensity points) and waveguide dimensions, by matching fiber graded index profiles and waveguide step profiles. The connection needs to be matched with center-to-center spacing (pitch) to assure that maximum offsets are not exceeded. This is accomplished by using micro ferrules (machined slots for pin alignment required) designed for small array coupling footprints. In addition, it is necessary to couple to waveguide arrays on a highdensity board with the several hundred interconnections using stacked waveguide films, and with a pitch less than the 250 micron limitation associated with standard optical fibers. Type Two uses I/O mirrors cut at 45 degrees to deflect waveguided light perpendicularly from waveguide films to or from guides, sources or detectors components. An example of a waveguide deflecting metallized mirror is shown is FIGURE 5. Typically, unguided light path distances here are approximately 50 microns. The mirror surfaces are usually metallized to ensure that high angle multimode propagated light is reflected and not passed through a total internal reflection (TIR) mirror (without metallization). Propagating angles with reasonable mode fill are likely to exceed the total internal reflection critical angle allowed. Applications include substrate-attached guides for flip-chips or access to overlying components and top-access configurations used with flexible jumpers and functional devices not attached to the substrate. These mirrors can be cut at 45 degrees by microtome (thin blade used in tissue cutting) or excimer laser on the film edge. For mirrors in the center of waveguide film sheets, excimer laser micromachining will MARCH 2008 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover1) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover2) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page 1) Printed Circuit Design & Fab - March 2008 - Contents (Page 2) Printed Circuit Design & Fab - March 2008 - Contents (Page 3) Printed Circuit Design & Fab - March 2008 - Our Line (Page 4) Printed Circuit Design & Fab - March 2008 - Our Line (Page 5) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - March 2008 - Around the World (Page 8) Printed Circuit Design & Fab - March 2008 - Around the World (Page 9) Printed Circuit Design & Fab - March 2008 - Around the World (Page 10) Printed Circuit Design & Fab - March 2008 - Around the World (Page 11) Printed Circuit Design & Fab - March 2008 - Happenings (Page 12) Printed Circuit Design & Fab - March 2008 - Happenings (Page 13) Printed Circuit Design & Fab - March 2008 - ROI (Page 14) Printed Circuit Design & Fab - March 2008 - ROI (Page 15) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 16) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 17) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 20) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 21) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 22) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 23) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 24) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 25) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 26) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 27) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 28) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 29) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 30) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 31) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 32) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 33) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 34) Printed Circuit Design & Fab - March 2008 - Ad Index (Page 35) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 36) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 37) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 38) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 39) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 40) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 41) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 42) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover4)
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