Printed Circuit Design & Fab - March 2008 - (Page 28) OPTICAL INTERCONNECT FIGURE 9. Schematic for daughter board to backplane/mother board 90 degree connectivity. FIGURE 11. Collection of connectorized optical links. FIGURE 12. Waveguide arrays configured for long backplane circuit board runs. FIGURE 10. Final configuration schematic for flexible positioning housing. through a mirror with a lens through-board interconnection. An example is shown in FIGURE 7, with a side view schematic showing the installation configuration. With lenses, unguided distances can be increased to greater than 1 mm. Lenses facilitate imaging of component I/O with the waveguides through the mirror. This lens waveguide array requires several precise alignment shims to span this distance, in order to couple precisely with the waveguides. Applications can include traversing between top and bottom substrate surfaces or through boards connecting sources and detectors to the waveguide arrays. The critical connectivity issue with Type Three is that alignment for waveguides, lens elements and components must be within a few microns to ensure low loss connectivity. Optical fiber to waveguide array interface is achieved with an MT-like ferrule or micro ferrule for the example shown, using a flexible link not attached to the substrate that bridges to the outside of the package. Waveguide assembly, including fiber interface, mirrors, and the lens unit has a system loss of less 28 than 1 dB (20%). The entire system loss is within operational specifications, including coupling from the four VCSELs through the system and back to four detectors. The final Stratos Optical Technologies TxRx unit (without cover) is shown in FIGURE 8. Alignment specs and tolerances for edge connections and mirrors are identical for this interconnect, including transmitter (Tx) and receiver (Rx) optimum-sized waveguides for high performance coupling to graded index fibers. Shown in FIGURE 9, the 60-micron guides are used for the receiver and the 30-micron guides for the transmitter. Type Four is based on board-to-board coupling for perpendicular connected substrates (as used for mother-todaughter boards) which is achieved with ferrules in latchable housings, using butt coupling multilayer waveguide arrays. The critical connectivity issues include the alignment and precision issues outlined in Type One (for MT ferule style connectivity). Particular emphasis should be placed on polymer waveguide-to-waveguide interconnection through the daughter board edge to backplane/mother board guide as depicted in Figure 9. To achieve daughter board-to-daughter board connectivity along the backplane, precisely arranged stacked guides and very high-density arrays are likely to be required. Direct zero air gap contact is desirable for the ferrule-to-ferrule interface. Spring-loaded compression combined with flex MARCH 2008 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover1) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover2) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page 1) Printed Circuit Design & Fab - March 2008 - Contents (Page 2) Printed Circuit Design & Fab - March 2008 - Contents (Page 3) Printed Circuit Design & Fab - March 2008 - Our Line (Page 4) Printed Circuit Design & Fab - March 2008 - Our Line (Page 5) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - March 2008 - Around the World (Page 8) Printed Circuit Design & Fab - March 2008 - Around the World (Page 9) Printed Circuit Design & Fab - March 2008 - Around the World (Page 10) Printed Circuit Design & Fab - March 2008 - Around the World (Page 11) Printed Circuit Design & Fab - March 2008 - Happenings (Page 12) Printed Circuit Design & Fab - March 2008 - Happenings (Page 13) Printed Circuit Design & Fab - March 2008 - ROI (Page 14) Printed Circuit Design & Fab - March 2008 - ROI (Page 15) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 16) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 17) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 20) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 21) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 22) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 23) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 24) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 25) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 26) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 27) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 28) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 29) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 30) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 31) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 32) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 33) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 34) Printed Circuit Design & Fab - March 2008 - Ad Index (Page 35) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 36) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 37) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 38) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 39) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 40) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 41) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 42) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover4)
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