Printed Circuit Design & Fab - March 2008 - (Page 30)

EMBEDDED CAPACITANCE Implementation of Buried Capacitance in HIGH-SPEED DESIGNS Embedded capacitance frees up the board surface for routing traces, can reduce the overall board size and can speed time to market. by JUN FAN, NORM SMITH, JIM KNIGHTEN, JOHN ANDRESAKIS, YOSHI FUKAWA and MARK HARVEY The integration of embedded capacitor technology is driven by the need to save board area and/or reduce board size, increase functionality, lower costs and improve electrical performance. It has been demonstrated that the performance of embedded capacitance laminate layers in a PCB stack up are more effective in high-frequency noise suppression than discrete surface mount technology (SMT) capacitors. There is however, little information regarding the number of discrete capacitors that can be safely removed by utilizing this technology. As other applications for incorpo- rating embedded capacitance layers are being examined (such as the modules used in cell phones and laptop PCs) the ability to predict the number of discrete decoupling capacitor components that can be safely removed is likely to be critical in the decision of whether or not to use the technology. One approach to determine this is to use the electrical performance simulation of boards with and without embedded capacitors. To further the knowledge in this area, additional data should be generated. The number of discrete components that the model predicts needs to be compared to those that can actually be removed from the board without a negative impact. With a good predictive model, the decision to utilize embedded capacitors can be simplified. Redesigning with Embedded Capacitance To determine the performance benefits of embedded capacitance, a power/ ground simulation tool was used to compare the impedance and resonances of the standard design with one using embedded materials of varying dielectric constant (Dk) and thickness. The goal of this project was to redesign a board with embedded capacitors and compare the performance to the standard design. The standard product was a 12layer PCB with two 1.5 V planes and one 3.3 V plane. The standard stack up is shown in FIGURE 1 on the left-hand side. To add the embedded capacitance material while maintaining the mechanical symmetry, a new 14-layer stack-up was used with two FaradFlex® thin-laminate cores added. The redesign is shown on the righthand side of Figure 1. The top FaradFlex® core is used for the 3.3 V supply, and the bottom one for the 1.5 V supply. The thickness of the 1.5 V/Ground plane pair in the center of the stack up remains approximately the same. Three versions of the new 14-layer PCBs were manufactured, in addition MARCH 2008 FIGURE 1. Adding embedded capacitance layers. 30 PRINTED CIRCUIT DESIGN & FAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008

Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.