Printed Circuit Design & Fab - March 2008 - (Page 31)

-20 -40 dB Ω dB -60 -80 BC12 BC12TM BC24 FR4 50 40 30 20 10 0 -10 BC12 BC12TM BC24 FR4 -100 -120 0.01 -20 -30 0.01 0.1 1 10 100 Frequency (MHz) 1000 10000 0.1 1 10 100 Frequency (MHz) 1000 10000 FIGURE 2. Measured bare board |S21|: 1.5 V/GND pair. FIGURE 3. Simulated bare board |Z11 : 1.5 V/GND pair. TABLE 1. DC capacitance measurements. PLANE PAIR 1.5 V/GND FR-4 (NF) 76.1 (75.8) 3.3 V/GND 21.2 (21.2) BC24 (NF) 179.5 (179.0) 323.8 (321.3) BC12 (NF) BC12TM (NF) 286.7 (266) 551 (541) 487 (478) 1148 (1082) to the standard 12-layer board. The new 14-layer PCBs were manufactured using BC24, BC12, and BC12TM materials as the thin laminate cores, respectively. These boards are denoted as BC24, BC12, and BC12TM in the descriptions and figures that follow. The standard 12-layer boards are denoted as FR-4 for simplicity. BC24 and BC12 are modified epoxy substrates that are 24 and 12 micrometers in thickness respectively. BC12TM is also a 12 micrometer material but has high Dk ceramic particles added to raise the Dk to 10 from the 4.4 of the unfilled products. The materials are formulated to insure durability during PCB processing. The copper foil is a special low profile version to minimize the chance of shorts or leakage. The material is manufactured and distributed under the Buried CapacitanceTM license of Sanmina-SCI Corporation. To evaluate the performance of the FaradFlex materials, the BC24, BC12, and BC12TM boards were populated only with bulk decoupling capacitors, and the FR-4 board was fully populated with MILLION GHz* * When tested with lab optimized and unrealistic PCB routings. My connectors are good to a My connectors are good to a BILLION GHz* TRILLION GHz* * When tested without thinking about the PCB Break-Out Region at all. My connectors are good to a My connectors are good to a GHz* * When tested with Final Inch® certiﬁed Break-Out Region PCB designs. 9 * When tested with lab optimized manufacturing processes and exotic materials. Samtec Final Inch® Break Out Region (BOR) PCB design recommendations that save design, development and validation time and resources and predict real-world performance expectations in real-world signal integrity applications. www.ﬁnalinch.com fina MARCH 2008 ® linch.com PRINTED CIRCUIT DESIGN & FAB 31 http://www.finalinch.com http://www.finalinch.com

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Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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