Printed Circuit Design & Fab - March 2008 - (Page 32)

-10 -20 -30 -40 dB -50 -60 -70 -80 BC12 BC12TM BC24 FR4 Noise Voltage (mV) 0.1 1 10 100 Frequency (MHz) 1000 10000 6 4 2 0 -2 -4 -90 -100 0.01 -6 0 0.5 1 1.5 2 2.5 3 Time (ns) 3.5 4 4.5 5 FIGURE 4. Measured bare board |S21|: 3.3 V/GND pair. 50 40 30 20 dB Ω 10 0 -10 -20 BC12 BC12TM BC24 FR4 FIGURE 6. Time-domain power bus noise: 1.5 V/GND pair, FR-4. 6 4 Noise Voltage (mV) 2 0 -2 -4 -30 -40 0.01 0.1 1 10 100 Frequency (MHz) 1000 10000 -6 0 0.5 1 1.5 2 2.5 3 Time (ns) 3.5 4 4.5 5 FIGURE 5. Simulated bare board |Z11|: 3.3 V/GND pair. FIGURE 7. Time-domain power bus noise: 1.5 V/GND pair, BC12. bulk and high-frequency SMT decoupling capacitors. Compared to the standard FR-4 boards, the embedded capacitance boards had 781 SMT capacitors removed. The decision to remove all the decoupling capacitors was based on the results of the simulations and that this methodology had proven effective in previous designs. The testing included swept-frequency S- and Z-parameter measurements for both the bare and populated boards, power bus noise measurements in both frequency and time domains, pre-EMI scan, and environment chamber testing. Good correlation of simulated to measured performance was recorded. Thin capacitor substrates do have an effect on the characteristics of power/ground planar power bus structures. In general, the voltages are more stable with greatly reduced resonances. By using thin core planes and simulation tools the number of discrete capacitors can be reduced, and electrical performance is improved. Besides reducing the number of discrete capacitors used, there is also a reduction in power/ground plane resonance that minimizes the amount of electro-magnetic radiation from the board. currently process 0.002 inch core materials should be able to process these materials with minor process/handling changes. Performance/DC Capacitance of Bare Boards The DC capacitance of the 1.5V/Ground pair, as well as the 3.3V/ Ground pair, was measured for all four types of the bare boards. Two methods were used, and the results were either directly obtained from an LCR meter or indirectly derived from vector network analyzer measurements. As shown in TABLE 1, the results from the two methods agree within less than 10% (results from the network analyzer are in parentheses in the table). The capacitance cores significantly increased the DC capacitance values (from between 60-80% for the 1.5V/GND plane pair and from 93-95% for the 3.3V/GND plane pair). The BC12TM cores achieved the largest capacitance values as expected. A large DC capacitance is beneficial for power bus as it can store more charge for logic transitions, as well as decrease power bus impedance at low frequencies. An interesting observation is that the DC capacitance values are larger for the 3.3 V/Ground pair than the 1.5V/ Ground pair in the embedded capacitance boards. That is because the bottom 1.5 V plane shown in is a split plane, and the area of the 1.5 V is only approximately one third of the total board area. Therefore, the increase in DC capacitance is less significant due to the reduced plane area. MARCH 2008 Product Build The newly designed 14-layer embedded capacitance PCB’s were manufactured using ZBC™ layer processing. Minor wet process allocations were made to process the thin cores along with a recommended 500-volt HiPot test for the cores prior to lamination and a final PCB 500-volt HiPot after test. All manufacturers that 32 PRINTED CIRCUIT DESIGN & FAB

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Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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