Printed Circuit Design & Fab - March 2008 - (Page 34)

60 50 40 30 20 10 Noise Voltage (dB) 60 50 40 30 20 10 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 Noise Voltage (dB) 00 FIGURE 9. Frequency-domain power bus noise: 1.5 V/GND pair, BC12. FIGURE 11. Frequency-domain power bus noise: 3.3 V/GND pair, BC12. 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 FIGURE 12. Simulation result for 3.3 V/GND plane between FR-4, BC24, BC12 and BC12TM. Noise Voltage (dB) FIGURE 10. Frequency-domain power bus noise: 3.3 V/GND pair, FR-4. blocking capacitor to prevent damage to the oscilloscope. FIGURE 6 shows the power bus noise voltage in the 1.5V/ Ground pair measured at one location on the FR-4 sample. FIGURE 7 shows the measurements for the BC12 boards. Similar timedomain performance was noted for the other capacitance materials. All of the materials produced a PCB with less noise than the standard FR-4 board. For the 1.5 V/GND pair, the peak-to-peak noise voltages are approximately the same for all types of the boards and dominated by the lower frequency envelope. The higher frequency noise for the 3.0 V/GRD pair is likewise reduced and the overall peak-to-peak noise voltage was lower than the FR-4 board. The embedded capacitance boards resulted in lower power bus noise. This was achieved when all the high-frequency SMT decoupling capacitors were removed. The redesigned boards functioned correctly with only the embedded capacitance layers and bulk decoupling capacitors. away by a built-in DC block. The results in the 1.5 V/GND pair in the frequency band from 10 MHz to 1 GHz are shown in FIGURE 8 and FIGURE 9, the FR-4 and BC12 boards, respectively. The corresponding 3.3 V/GND pair results are presented in FIGURE 10 and FIGURE 11 for the same boards. It is quite difficult to draw definite conclusions from these frequency-domain results due to their complexity. Although the noise voltages at some frequencies are lower in the embedded capacitance boards (for example, at the three peaks between 200 MHz and 500 MHz as shown in Figure 8 and Figure 9), the noise magnitudes at some other frequencies are actually higher. Measurements at frequencies higher than 1 GHz may assist in the development of insight. Simulation Results Simulation was performed to compare the result with actual board measurement utilizing EMIStream developed by NEC. This simulation calculates impedance |Z11| of a power plane based on PEEC (Partial Element Equivalent Circuit Model) method and Spice simulation. The parameters for this target PCB such as thickness between power and ground plane, Dk and copper thickness have been set prior to running simulation. Also the excitation point has been set at the exact same point as where the actual board measurement was probed. The simulation results for 3.3V/GND plane shown in FIGURE 12 compare the results of standard FR-4 boards to the BC24, BC12 and BC12TM boards. As shown in Figure 5, at the low frequencies MARCH 2008 Product Performance/Frequency-Domain Power Bus Noise Measurements The power bus noise at the same port locations was measured in the frequency domain as well. An Agilent E7404A EMC Analyzer (a spectrum analyzer) was used with a resolution bandwidth of 10 KHz. Again the DC component was filtered 34 PRINTED CIRCUIT DESIGN & FAB

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Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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