Printed Circuit Design & Fab - March 2008 - (Page 38) TABLE 1. Elemental coating composition. XPS SURFACE COMPOSITION OF ALT. OXIDE COATING ATOMIC % Peel Strength, lb/in Elements Detected As treated Post treated C 62 53 Cuprous Cu+ As treated Post treated 64 80 O 13 16 Cupric Cu+2 36 20 Cu 8.6 26 Cu+/+2 Ratio 1.8 4.0 N 17 5 Impact of Sequential Lamination Peel Strength vs SBU Multi-Lamination (Phenolic Cure 175 Tg) 6.00 DSTF 1st Press DSTF 2nd Press 5.50 DSTF 3rd Press 5.00 4.50 4.00 3.50 3.00 0.89 1.14 1.40 1.65 TABLE 2. Some factors influencing delamination. REFLOW ■ Excessive peak temperatures ■ Incorrect profiles/rework Etch volume, Microns / pass FIGURE 3. Peel strength change with SBU. MATERIAL ■ Incorrect material choice, Tg or compatibility ■ Breakdown of the dielectric material/quality LAMINATION FACTORS ■ ■ ■ ■ review in order to deliver even greater performance. This improvement is needed to meet the requirements associated with the sequential lamination cycles applied in some buildup processes, and to withstand the extreme thermal stresses incurred in lead-free assembly and re-work. Incomplete lamination Excessive lamination temperatures Excessive moisture Incorrect Tg achieved The Oxide Replacement Process The peroxide-sulfuric oxide replacement process is controlled by a primary organic material that modifies the etching mechanism to provide a consistent, highly textured, and characteristic surface structure. Not only does the primary organic additive accelerate the etch and modify the copper surface, but it also chemically combines with the copper to produce the characteristic organo-copper coating. This organic coating is based mainly on cuprous (Cu+) oxide but also contains some cupric (Cu+2) oxide. These give the conversion coating its characteristic red-brown color. The schematic formation of the alternative oxide coating is shown in FIGURE 1. It is well understood that a cuprous-rich oxide coating typically delivers higher bond strength in the prepreg to copper layer. Cuprous oxide is more thermally stable than cupric oxide. In addition, a cuprous rich oxide has a higher chemical resistance to PTH chemistries, which can give rise to “pink ring” through the attack and separation of the oxide planes around the periphery of the holes. This chemical resistance is critical not only for the metallization of high aspect ratio through-holes, but more importantly for the landing pads on blind microvias. It is possible to post treat the oxide conversion coating using an alkaline process to remove the less resistant cupric oxide. Such post treatment can increase the peel strength of the coating by 10 to 15%, but it does not improve the resistance to thermal delamination. The elemental analysis is shown for both a standard and a post-treated coating. FIGURE 2 shows the actual XPS spectra of the as-produced coating and post-treated coating (following a proprietary post dip). As would be expected, the post-treated layers have a lighter more-reddish appearance, indicative of the increased cuprous oxide content. This coating composition is also outlined in TABLE 1. BOARD CONSTRUCTION / DESIGN FACTORS ■ Inner layer build/copper distribution ■ Pre-preg build up/coarse glass interface/resin starvation ■ Hole cluster density COPPER: DIELECTRIC BOND ■ Inadequate or incomplete oxide coverage ■ Contamination of oxide or core dielectric ■ Breakdown of oxide coating The Challenges The current peroxide-sulfuric oxide replacement process work based on a “controlled etch” mechanism that typically removes 45 to 75 microinches (1.1 to 1.9 µm) of copper. Innerlayers are first cleaned and then conditioned in an alkaline medium, rinsed, and then are processed in the peroxidesulfuric micro-etching bath. The copper saturation capacity of this bath is limited and has historically been on the order of 18 to 22 g/L. Over the past three years, this technology has improved, allowing a higher solution capacity of 50 g/L in high-volume production environments. This capacity increase has been largely the result of improved copper solubility coupled with greater process stability. The requirements for the high-yield production of controlled impedance and fine line innerlayers also call for further reductions in the copper etch levels. This low etch approach greatly benefits high frequency signal integrity by significantly reducing the “skin-effect” caused by a deep etch profile. Reduced etching is often at odds with improved bond performance. The need to improve bonding performance to meet the demands of new resin systems and RoHS assembly temperatures, with minimal removal in the order of 35 to 45 microinches (0.9 to 1.1 µm) of copper, has become a benchmark for a “best in class” process. Within this challenge, higher values for peel strength and increased T260 and T288 (time-to-delamination) values are continually sought, with the process undergoing continuous 38 The Effect of Sequential Build Increasingly, PCB construction, especially for thin card mobile or PDA-type products, is produced using sequential lamination techniques. Here, each lamination cycle adds additional and cumulative thermal stress to the innerlayer bond within the core construction. Depending on the lamination temperature, MARCH 2008 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover1) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover2) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page 1) Printed Circuit Design & Fab - March 2008 - Contents (Page 2) Printed Circuit Design & Fab - March 2008 - Contents (Page 3) Printed Circuit Design & Fab - March 2008 - Our Line (Page 4) Printed Circuit Design & Fab - March 2008 - Our Line (Page 5) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - March 2008 - Around the World (Page 8) Printed Circuit Design & Fab - March 2008 - Around the World (Page 9) Printed Circuit Design & Fab - March 2008 - Around the World (Page 10) Printed Circuit Design & Fab - March 2008 - Around the World (Page 11) Printed Circuit Design & Fab - March 2008 - Happenings (Page 12) Printed Circuit Design & Fab - March 2008 - Happenings (Page 13) Printed Circuit Design & Fab - March 2008 - ROI (Page 14) Printed Circuit Design & Fab - March 2008 - ROI (Page 15) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 16) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 17) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 20) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 21) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 22) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 23) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 24) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 25) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 26) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 27) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 28) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 29) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 30) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 31) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 32) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 33) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 34) Printed Circuit Design & Fab - March 2008 - Ad Index (Page 35) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 36) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 37) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 38) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 39) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 40) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 41) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 42) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover4)
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