Printed Circuit Design & Fab - March 2008 - (Page 39)

INNERLAYER PROCESSING Simple Delamination Test Vehicle RCC Foil Alternative Oxide Prepreg Cu Cladding Alternative Oxide Core FIGURE 6. Simple delamination test vehicle. FIGURE 4. Failure of copper-to-dielectric interface. FIGURE 5. Failure within the dielectric itself. TABLE 3. Summary of Taguchi optimization for the HCC alternative oxide. PARAMETER Surfactant A (mg/L) Surfactant B (ml/L) Organic 1 (ml/L) Grain Refiner (ppm) Organic 2 (ml/l) Oxidizer (ml/l) Acid I (ml/l) Peel Strength (N/mm) IR-Reflow (T280) (Cycles) Color (Index) ALPHAPREP STD 100% 100% 100% 100% 100% 100% 100% 0.7 3 7.5 HIGHEST PEEL STRENGTH 125% 156% 111% 108% 300% 117% 150% 1.2 11 10 HIGHEST IR REFLOW 104% 156% 100% 115% 200% 117% 150% 1.1 13 10 OPTIMIZED 100% 150% 100% 108% 200% 117% 113% >1.1 >10 10 layer (adhesive failure), or within the dielectric itself (cohesive failure). Examples of these two conditions are shown in FIGURE 4 and FIGURE 5, respectively. Product Improvement Approach Following the transition to lead-free, the development group had already completed work designed to provide alternative oxide products with improved high temperature performance. An older, first generation, 25 g/L low copper capacity product (LCC) with improved thermal stabilization was used as the benchmark. This LCC prototype product had a demonstrated capability to withstand extended IR lead-free reflow cycles, and was developed specifically for critical high-end applications. For comparison, a 50 g/L high copper capacity (HCC)/ low etch product was used to address the requirements of higher signal integrity, improved environmental capability (reduced waste), and lower cost of ownership. (typically 190 to 200˚C), this can progressively reduce bond strength prior to final soldering, hence increasing requirements for improved thermal integrity. The negative impact on peel strength caused by sequential bonding cycles is shown in FIGURE 3. The discussion of the repeated thermal cycles used in SBU fabrication must include consideration of the added effects of the higher temperatures seen in lead-free assembly. Exposure to multiple thermal cycles can have a cumulative effect on bond integrity. high cluster-densities of small holes, can be especially vulnerable. Delamination can be triggered by a combination of many factors, and the first step in determining root cause is to answer the key question – where is the delamination occurring? The problem is typically diagnosed by using cross section techniques to determine if the breakdown is between the copper-to-dielectric Impact of Lead-Free Assembly on the Alternative Oxide Bond The IR reflow soldering cycles used in assembly apply a large amount of stress to both the core and sequential build layers. Although the peak temperatures are targeted at 245 to 250˚C, they can clearly overshoot these values, potentially rising to 260˚C or more. At this point, or during the subsequent solderwave application, the boards can fail due to delamination. Large copper areas, especially those carrying very MARCH 2008 PRINTED CIRCUIT DESIGN & FAB 39 http://www.pcb-pool.com/ppus/info.html?PHPSESSID=7df48fa7c977776045ff8d4b24a70fc7 http://www.free-pcb-software.com http://www.pcb-pool.com/ppus/info.html?PHPSESSID=7df48fa7c977776045ff8d4b24a70fc7

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008

Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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