Printed Circuit Design & Fab - March 2008 - (Page 40) INNERLAYER PROCESSING Bonding Test IR Reflow Profile for Element Weigth Percentage 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 Temperature (°C) 0 25 50 75 100 125 150 175 200 225 250 275 300 Time (seconds) FIGURE 7. Stressed IR reflow profile. Carbon Nitrogen Oxygen 18 16 14 12 10 8 6 4 2 0 230 235 240 245 250 255 260 265 270 275 Temperature (˚C) FIGURE 8. Auger results v temperature for the improved HCC technology. The HCC technology used organic stabilization similar to the LCC product and had an already demonstrated better performance for peel strength and thermal shock resistance in high volume production environments. The defined approach was to further optimize the HCC technology through more exhaustive thermal stability testing, by using extensive L9 and L18 Taguchi methodology. To test the product improvements against the benchmark, a rigorous testing protocol was developed. It included a test vehicle (FIGURE 6) that was based on a six-layer board with a rigid FR-4 based four-layer core. The FR-4 material was standard 150˚C Tg epoxy. To simulate a sequential build-up product, resin coated copper was added as additional layers (one and six) to the four-layer core. Prior to lamination of the resin coated copper foil, the core layers two and five were electroplated with a standard acid copper process to simulate a buried via construction. This build allowed the examination of the effects of in-house electroplated copper on bond strength. During the testing process the test vehicles were subjected to high stress thermal excursions of 270 to 280˚C in an IR reflow chamber. The failures that occurred could be found in either the central core or within the surface layers. The profile of the IR reflow excursion is shown in FIGURE 7. Initial Benchmarking results Using the IR profile described, copper innerlayers treated with the HCC process were subjected to the reflow cycle. Where older generation technology showed significant color change and pronounced thermal breakdown effect at temperatures over 260˚C, the HCC process was able to withstand the peak of 270˚C without any pronounced change of color. In addition, Auger studies were used to determine the effects of temperature on the organo-coating. The Auger tests showed no significant loss (evaluating the elements Carbon and Nitrogen) or oxidation of the coating. Further, significant improvements in stability were seen over the lower soldering temperature range. No perceptible change or evidence of oxidation was experienced. The Auger results are shown in FIGURE 8. The improved HCC technology also demonstrated a 6 to 15% improvement in peel strength of the coated layers. These results represent a major step forward in improving the coating’s thermal resistance. Furthermore, at 270˚C the 40 HCC technology was able to withstand an average of 1.5 additional cycles before failure due to delamination compared to the first generation processes. Having achieved very satisfactory improvement with the high copper capacity formulation, the next step was to optimize the formula for thermal performance using the Taguchi approaches previously described. The applied series of test arrays included a) the primary and secondary inorganic acids (that influence the etching characteristic and solubilize the copper); b) the organic components (that drive the modified etch reaction rate, produce the organo conversion coating, and stabilize the process and the coating); c) the grain refiner (essentially a chloride based species), and finally; d) the oxidizing agent – hydrogen peroxide (also drives the reaction-rate and texture depth). The studied responses were coating color, etch-rate, pull/ peel strength after coating, and most importantly, the resistance to delamination using multiple IR reflow cycles with peak temperatures of 270˚C and 280˚C respectively. Details of some of the individual component plots, drawn from one of the later L18 arrays employed, are illustrated in FIGURE 9. As expected, varying levels of response, and some interactions, were seen with many of the parameters employed. The findings were interesting for several reasons. It was determined that only one organic additive parameter significantly affected the color of the coating, but several of the additives had a significant influence on the delamination resistance. By contrast, the peel strength was mainly impacted by two significant factors. Interestingly, all the factors that positively influenced the thermal performance also improved the primary peel strength results. These factors also contributed to a good aesthetic coating color and appearance. This can be seen in the similarity of the displayed Taguchi responses that moved largely in unison. This facilitated the completion of an optimized HCC product for the confirmation runs. A summary of the Taguchi optimization is shown in TABLE 3. The confirmation testing showed an expected and very positive gain with the achievement of more than 10 IR reflow cycles without failure, based on the aggressive test vehicle and profiles involved. The resulting confirmation runs for delamination, as compared to the first generation technology and HCC standard benchmarks are shown in FIGURE 10. MARCH 2008 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover1) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover2) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page 1) Printed Circuit Design & Fab - March 2008 - Contents (Page 2) Printed Circuit Design & Fab - March 2008 - Contents (Page 3) Printed Circuit Design & Fab - March 2008 - Our Line (Page 4) Printed Circuit Design & Fab - March 2008 - Our Line (Page 5) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - March 2008 - Around the World (Page 8) Printed Circuit Design & Fab - March 2008 - Around the World (Page 9) Printed Circuit Design & Fab - March 2008 - Around the World (Page 10) Printed Circuit Design & Fab - March 2008 - Around the World (Page 11) Printed Circuit Design & Fab - March 2008 - Happenings (Page 12) Printed Circuit Design & Fab - March 2008 - Happenings (Page 13) Printed Circuit Design & Fab - March 2008 - ROI (Page 14) Printed Circuit Design & Fab - March 2008 - ROI (Page 15) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 16) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 17) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 20) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 21) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 22) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 23) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 24) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 25) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 26) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 27) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 28) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 29) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 30) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 31) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 32) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 33) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 34) Printed Circuit Design & Fab - March 2008 - Ad Index (Page 35) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 36) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 37) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 38) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 39) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 40) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 41) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 42) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover4)
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