Printed Circuit Design & Fab - March 2008 - (Page 41) INNERLAYER PROCESSING Peel Strength 1.0 Grain Refiner 0.9 0.8 0.7 0.6 0.5 0.4 0.3 60 70 80 90 100 ppm 1.0 Surfactant 2 0.9 0.8 0.7 0.6 0.5 0.4 0.3 ml/L IR- Reflow T280 10 Grain Refiner 9 8 7 6 5 4 3 2 ppm 10 Surfactant 2 9 8 7 6 5 4 3 2 ml/L Color Cycles to Delamination 12 280°C 10 8 6 4 2 0 First Generation HCC HCC Improved FIGURE 10. Confirmation run – IR reflow delamination tests. 270°C 10 Grain Refiner 9 8 7 6 5 4 3 2 ppm 10 Surfactant 2 9 8 7 6 5 4 3 2 ml/L N/mm Cycles N/mm Cycles Index Index Peel Strength N/mm Index 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Acid 1 IR- Reflow T280 Color ml/L Oxidizer ml/L Acid 1 Acid 1 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 0 20 40 60 80 0 20 40 60 80 ml/L ml/L Oxidizer Oxidizer 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 ml/L ml/L Index Index FIGURE 9. Taguchi responses on development optimization. Conclusions The worked described in this article has encompassed a long period of design, development and testing, and was carried out over a three-year period. Along the way, a lot of input has been received from the market, in terms of both defining the challenge and applying best practices to meet the growing industry requirement for improved PCB thermal resilience. Several leading PCB fabricators have made significant progress in selecting improved materials and incorporating better lamination and process procedures, all of which open up the operating window for more demanding products. From this work, it is clear that many factors can significantly and adversely outweigh the alternative oxide contribution in achieving the balance required for bullet-proof performance. To play its part, this study has been focused solely on finding ways to improve the performance and contribution of the alternative oxide bonding technology. The goal has been to provide a robust process with a wider operating window offering better thermal resilience. Conclusions from this specific study can be summarized as follows. Delamination failures due to lead-free thermal stress can be caused by many factors, most significantly those involving the dielectric materials and the lamination process. In the broader context, industry opinion is that the alternative MARCH 2008 oxide process has a smaller impact than other material factors in delamination. Improving the process can, however, make an important contribution, especially for PCBs with large copperto-dielectric bonding areas such as internal ground planes. This can be seen with the older generation alternative oxide bonding technology, which cannot consistently meet the increasing industry requirement of highly advanced and performance sensitive designs for IR reflows without blistering, delamination or related electrical failure in lead free applications. The stability of the respective organo-metallic conversion coating diminishes at 260˚C, where bonding performance decreases with each successive thermal excursion, leading to potential delamination issues. The use of proprietary post treatments, which increase the cuprous oxide ratio can provide improvements to peel strength, but do not necessarily solve the thermal resilience challenge. One conclusion that can be drawn from this work is that the industry-standard pull/peel strength measure cannot adequately predict in-process bond strength, or a PCB’s resistance to delamination under thermal stress. Improved LCC (low copper capacity) and HCC (high copper capacity) products have already demonstrated higher thermal stability than their earlier counterparts, along with greater capability to withstand multiple lead-free reflows at inflated peak IR reflow temperatures of 270 to 280˚C. The laboratory work described in this article establishes that an optimized HCC process can also more effectively meet the 10 plus multiple reflow requirements associated with sequential lamination and RoHS assembly simulation. Product design specifications for a low-etch attribute (1.0 to 1.2 µm) for controlled impedance, fine line integrity and improved high frequency signal integrity have been key factors in this work. Maintaining the required high copper capacity of 50 g/L delivers reduced environmental impact and the lowest cost of ownership. PCD&F N/mm Cycles Cycles DR. ABAYOMI I. OWEI is president/principal research scientist at Avo Tech International Inc.; Abayomi_Owei@Avotechinternational.com. DR. JEAN RASMUSSEN is R&D manager, PWB metallization, at Enthone; jrasmussen@cooksonelectronics. com. DR. AXEL DOMBERT is European technical manager, PWB products, at Enthone; adombert@cooksonelectronics. com. DANIS ISIK is a research scientist, PWB products, at Enthone; disik@cooksonelectronics.com. DAVID ORMEROD is business director, PWB metallization, at Enthone; dormerod@ cooksonelectronics.com. PRINTED CIRCUIT DESIGN & FAB 41
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover1) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover2) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page 1) Printed Circuit Design & Fab - March 2008 - Contents (Page 2) Printed Circuit Design & Fab - March 2008 - Contents (Page 3) Printed Circuit Design & Fab - March 2008 - Our Line (Page 4) Printed Circuit Design & Fab - March 2008 - Our Line (Page 5) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - March 2008 - Around the World (Page 8) Printed Circuit Design & Fab - March 2008 - Around the World (Page 9) Printed Circuit Design & Fab - March 2008 - Around the World (Page 10) Printed Circuit Design & Fab - March 2008 - Around the World (Page 11) Printed Circuit Design & Fab - March 2008 - Happenings (Page 12) Printed Circuit Design & Fab - March 2008 - Happenings (Page 13) Printed Circuit Design & Fab - March 2008 - ROI (Page 14) Printed Circuit Design & Fab - March 2008 - ROI (Page 15) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 16) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 17) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 20) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 21) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 22) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 23) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 24) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 25) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 26) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 27) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 28) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 29) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 30) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 31) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 32) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 33) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 34) Printed Circuit Design & Fab - March 2008 - Ad Index (Page 35) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 36) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 37) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 38) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 39) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 40) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 41) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 42) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover4)
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