Printed Circuit Design & Fab - March 2008 - (Page 48)

BGA Fanout Patterns, Part 1 Successful fanout solutions provide escape routing for a combination of serial and parallel nets. THE EFFECTIVENESS OF a fanout pattern on large BGAs contributes significantly to the route-ability of a design, which impacts the layer CHARLES count and affects PFEIL the cost of the board fabrication. The fanout of a BGA is only a part of the routing solution, which may also include escape traces and general interconnect routing of the pins. The goal of the BGA fanout effort should be to eliminate the BGA routing as the primary contributor to increasing layer count while maintaining signal integrity and fabrication yield requirements. In a theoretical approach to BGA breakout, the BGA is analyzed outside the context of a real design. This kind of solution is a mathematical excercise in layer reduction that makes unrealistic assumptions and disregards SI requirements. Unfortunately, reality requires much more than just a mathematical solution. Deriving fanout patterns in a theoretical realm can actually be fairly simple, but finding effective fanout patterns when all the design and packaging challenges must be considered is a much more difficult problem. It would be ideal to have power and ground pins only in the center of a BGA, however, power integrity requires they also be distributed among the signal pins. This distribution is rarely in neat columns and rows, which would open up considerable routing space. FIGURE 1 shows an ideal distribution of ground pins (green). If the BGA had ground pins aligned this way, and if the mount layer was a GND plane, then you would see additional room made available on the inner routing layers. Unfortunately, most FPGA vendors distribute the power and ground pins around the BGA or use some pattern other than columns and rows. The purpose of distributing power and ground pins is to improve the power integrity. Xilinx often uses a “Sparse Chevron” pattern as shown in FIGURE 2. In this figure the ground pins are green and the power pins are brown. There may be some ASICs that have power and ground pins aligned in columns and rows, however, such an ideal condition is not common, and therefore effective fanout and routing solutions must incorporate other ways to reduce the layer count. Most large BGAs have a combination of serial and parallel nets that must be routed as differential pairs and single-ended nets (respectively). Some FPGAs also allow for nets to be programmed as either serial or parallel. These devices support multiple I/O performance standards that could require differential routing. Differential pairs and single-ended nets require different trace widths and spacing to maintain desired impedance, and although it is possible to use the same spacing rules inside the BGA area, impedance discontinuity may become significant in some high-speed circuits. For example, it is common to have a target of 50 Ω for single-ended nets and 100 Ω for differential pairs. Of course the stack up thicknesses and materials will affect the impedance; yet it is common to see a 0.15 mm (6th) for differential pair spacing while single-ended nets can have 0.1 mm (4th). Actual trace widths and clearances will vary depending on the specific high-speed and fabrication requirements for each design. If the fanouts are positioned such that differential pairs need to be split to maintain the trace width and clearance rules, that could also cause significant signal integrity problems, as illustrated in FIGURE 3. Summarizing, a theoretical fanout and breakout solution that does not take into consideration the potential for varied trace widths and clearances is not very useful. The problem becomes even more difficult when each I/O pin or bank of pins can be programmed to require either differential pair or single-ended routing. An effective fanout solution that enables the most efficient escape routing should be flexible enough to support the trace width and clearance requirements for a mixture of serial and parallel nets. PCD&F CHARLES PFEIL is a product marketing director for Mentor Graphics, Systems Design Division; charles_pfeil@mentor.com. FIGURE 1. Alignment of ground pins. 48 FIGURE 2. Xilinx sparse chevron pattern for power and ground pins. FIGURE 3. Splitting of differential pairs in BGA fanout via array. MARCH 2008 PRINTED CIRCUIT DESIGN & FAB

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Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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