Printed Circuit Design & Fab - April 2008 - (Page 2)

APRIL 2008 • VOL. 25 • NO. 4 FEATURES Packaging innovations like this tiny SiP , an integrated passive network with integrated passive devices and thin-film build-up passive elements, can overcome CMOS scaling limits until new materials and architectures can be developed and implemented. Photo courtesy of Fraunhofer-IZM. 24 DfM Improving Fabrication Yields by Design The PCB designer is the architect for improved PCB yields. by ZULKI KHAN 27 SI OPTIMIZATION Solve Design Problems with Signal Integrity Optimization POINT OF VIEW 4 OUR LINE Defining ’green.‘ Optimization routines save time by using automated methods to determine if performance goals are met. by PAT ZABINSKI, BEN BUHROW, BARRY GILBERT, and ERIK DANIEL Kathy Nargi-Toth 16 32 IMAGING ROI Picking a winning emerging technology can maximize profitability. Laser Direct Imaging Made Easy With over 400 installations worldwide, LDI is gaining global market acceptance. by GUY ALON and DR. RALPH BIRNBAUM Peter Bigelow 18 TIP JAR Education is key to a successful career, so be a lifelong learner. 36 INNERLAYER FABRICATION Troubleshooting the Innerlayer Process Identifying and maintaining proper process controls is key to improving innerlayer yields. by BETTY XIE and SIMON LEE Susy Webb 20 INTERCONNECT STRATEGIES Mathematical tools such as Mathcad can solve a wide range of SI problems. 40 PACKAGING DEVELOPMENTS SIPS GIVE MORE TO MOORE SiP-based system-level integration resolves CMOS scaling limits. by DR. W.R. BOTTOMS Dr. Abe (Abbas) Riazi 22 POSITIVE PLATING Maintaining process chemistry can alleviate plating problems. Michael Carano 48 DEPARTMENTS 6 10 BGA BULLETIN Through-vias provide low fab costs but can limit routing density. MARKET WATCH AROUND THE WORLD 14 43 HAPPENINGS OFF THE SHELF 44 47 MARKETPLACE AD INDEX Charles Pfeil Circuits Assembly Online COMPONENT PACKAGING circuitsassembly.com (PoP) are being developed to accommodate the advances. by FRANK Y. YUAN, PH.D. and RICHARD CRISP BETTER MANUFACTURING Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules DDR2 pushed memory clock frequencies to 400 MHz and data rates to 800 Mbps. DDR3 further pushes clock frequencies to 800 MHz while DDR4 up to 1.6 GHz. New packaging technologies such as die stacking and package-on-package Black Pad – A Scourge On Your Boards ENIG’s potential failure mechanism can reside randomly and unpredictably. by PHIL ZARROW POSTMASTER: Send address changes to PRINTED CIRCUIT DESIGN & FAB, P.O. Box 35646, Tulsa, OK 74153-0646 http://www.circuitsassembly.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - April 2008

Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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