Printed Circuit Design & Fab - April 2008 - (Page 20) Signal Integrity Applications of Mathcad, Part 1 Mathematical tools such as Mathcad can solve a wide range of SI problems. MATHCAD IS SOFTWARE with powerful capabilities to manipulate equations, numbers, text and graphs. The mathematical formulae and numerical values can be presented in an easy to read fashion. Mathcad allows graphics and text to be incorporated throughout the document, and if desired, the resultant files can be saved in DR. ABE (ABBAS) HTML format for posting to a website. RIAZI Mathcad has proven invaluable for a wide range of engineering designs and can be used in some interesting signal integrity applications1,2,3. For example, Johnson et al1,4, presents Mathcad computations for DC copper resistance, capacitance of parallel plates, inductance of circular loops, coaxial cables, microstrip lines, and forward and inverse Fourier Transform (i.e., FFT and IFFT). Use of this software for Fourier transformations and square wave decomposition is also discussed by Brooks2, and application of Mathcad for simulating single-ended and differential pair high-speed topologies are demonstrated by Norte3. As an example, let us apply Mathcad to analyze the asymmetric stripling configuration depicted by FIGURE 1. For asymmetric stripline (also referred to as offset stripline) the signal layer is sandwiched between two plane layers, but it is closer to one plane than the other (i.e., H1 not equal H). Setting H1=H leads to case of centered (or balanced) stripline. FIGURE 2 illustrates Mathcad calculations for characteristics impedance Z0 and propagation delay (Tpd). The parameters Er, H, H1 and W are defined at the top of Figure 2. The formulae for Z0 and Tpd are EQUATIONS 1 and 2, respectively. It illustrates that for Er = 4.2, H = 5 mils, H1 = 8mils, W = 6 mils and T = 0.7 mils, Z0 = 43.06 FIGURE 1. Asymmetric stripline geometry. Er := 4.2 Z0 := H := 5 H1 := 8 Ohms and Tpd = 2.084 ns/ft. In Mathcad files, parameter values can be easily altered to examine what happens to all variables and the graphs that depend on them. For example, setting Er = 4.0, H = 6 mil, H1 = 10 mil W = 5 mil T = 1.4 yields Z0 at 52.7 Ohms, and Tpd at 2.034 ns/ft. The analytical technique for determining impedance is less accurate than using a field solver5. Yet an analytical approach provides an efficient means for Z0 computations and can furnish useful insight regarding effects of the various parameters that affect impedance. Mathcad allows the incorporation of text, formulae, pictures, equations and graphs in the same document. This feature is demonstrated in the next example involving via inductance. Every via has a parasitic capacitance and inductance. The via inductance is often more critical (to digital design) than its capacitance. The parasitic inductance associated with vias can degrade signal integrity6 and reduce effectiveness1 of the power supply bypass capacitors. Via inductance is also important in the analyses of power distribution network (PDN) since it increases the impedance between source and load7. An example of calculating via (partial) inductance using Mathcad is illustrated below: Equation for L(h) in FIGURE 3 is an accurate expression for an isolated via (distanced away from other vias). When there are other vias nearby, the mutual inductance must also be taken into account7. Generally, Mathcad evaluates each statement in the program in sequence8, however, there are times when it is desirable to evaluate statements only when a particular condition is satisfied. This can be achieved by incorporating “if” statements. As an example, the Serial Attached SCSI (SAS) channel insertion loss formula9 will be evaluated utilizing this Mathcad feature. Transmission line losses can affect the h := 50, 100, 1,000 L(h) := 5.08 • h • 1n 4 • d := 12 Where h is via length and d is via barrel diameter. When h and d are in mils, L(h) is in pH. 1 • 105 ( ( h )+ 1) d W := 6 T := 0.70 ( )[ [ 80 • 1n 1.9 • (2 • H + T) (0.8 • W + T) Er ]] ( H • 14 • H1 ) Via pad EQ. 1 EQ. 2 Via barrel 1 • 104 L (h) 1 • 103 Tpd := 1.017 Er H, H1, W and T are in mils, Z0 is in Ohms, and Tpd is in ns/ft Z0 = 43.06 Ohms Tpd = 2.084 ns/ft 100 10 100 h FIGURE 3. Computation of Via inductance applying Mathcad. APRIL 2008 1 • 103 FIGURE 2. Z0 and Tpd computation for offset stripline utilizing Mathcad. 20 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 - (Page Belly1) Printed Circuit Design & Fab - April 2008 - (Page Belly2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover1) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page 1) Printed Circuit Design & Fab - April 2008 - Contents (Page 2) Printed Circuit Design & Fab - April 2008 - Contents (Page 3) Printed Circuit Design & Fab - April 2008 - Our Line (Page 4) Printed Circuit Design & Fab - April 2008 - Our Line (Page 5) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 8) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 9) Printed Circuit Design & Fab - April 2008 - Around the World (Page 10) Printed Circuit Design & Fab - April 2008 - Around the World (Page 11) Printed Circuit Design & Fab - April 2008 - Around the World (Page 12) Printed Circuit Design & Fab - April 2008 - Around the World (Page 13) Printed Circuit Design & Fab - April 2008 - Happenings (Page 14) Printed Circuit Design & Fab - April 2008 - Happenings (Page 15) Printed Circuit Design & Fab - April 2008 - ROI (Page 16) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast1) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast2) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast3) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast4) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast5) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast6) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast7) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast8) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast9) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast10) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast11) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast12) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast13) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast14) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast15) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast16) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert1) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert2) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert3) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert4) Printed Circuit Design & Fab - April 2008 - ROI (Page 17) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 18) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 19) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 20) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 21) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 22) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 23) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 24) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 25) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 26) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 27) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 28) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 29) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 30) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 31) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 32) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 33) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 34) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 35) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 36) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 37) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 38) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 39) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 40) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 41) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 42) Printed Circuit Design & Fab - April 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - April 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover4)
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