Printed Circuit Design & Fab - April 2008 - (Page 21) amplitude of high-speed signals and cause ISI5,10. Hence, when designing or testing a high-speed channel, it is crucial to consider the loss specifications. For instance, the loss budget for PCI Express Gen1 is specified as 13.2 dB at a frequency of 1.25 GHz. For SAS, the magnitude of insertion loss (SDD21) is given by a set of equations that can be analyzed using Mathcad as shown by FIGURE 4. Above examples demonstrate that Mathcad offers powerful capabilities for analyzing and solving signal integrity problems. Additional mathematical SI applications will be explored in Part 2 of this article. PCD&F DR. ABE (ABBAS) RIAZI is a senior staff electronic design scientist with Broadcom Corp. in Irvine, CA and can be reached at ariazi@broadcom.com. SAS channel insertion loss (within frequency range of 50 MHz to 5.0 GHz): f in Hz f := 50.00 • 106, 51.00 • 106 5 • 109 SDD21(f) := -10.884 if f > 3 • 109 -20 • log (2.71828) • [(6.5 • 10-6 • f 0.5) + (2 • 10-10 • f) + (3.3 • 10-20 • f2)] otherwise SDD21(f) (dB) 1 • 109 2 • 109 3 • 109 f (Hz) 4 • 109 5 • 109 FIGURE 4. Calculation of SDD21 magnitude in dB for SAS (3.0 Gb/s). REFERENCES 1. Howard Johnson and Martin Graham, “High-Speed Digital Design: A Handbook of Black Magic” Prentice Hall, 1993, PP 258-260, PP , . . 409-439. 2. Douglas Brooks, “Signal Integrity Issues and Printed Circuit Board Design” Prentice Hall, 2003, PP 18-21. , . 3. David Norte, “ Learn Signal Integrity Design Principles With Mathcad” , The EMC, Signal and Power Integrity Institute, 2005, PP 5-29, PP . . 41-48. 4. Howard Johnson and Martin Graham, “ High-Speed Signal Propagation: Advanced Black Magic” Prentice Hall, 2003, PP 249-250. , . 5. Eric Bogatin, “Signal-Integrity Simplified” Prentice Hall, 2004, P 257. 262, PP 334-335. . 6. Stephen H. Hall, Garrett W. Hall, James A. McCall, “High-Speed Digital System Design A Handbook of Interconnect Theory and Design Practices” John Wiley & Sons Inc., 2000, PP 102-104. , . 7. Istvan Novak and Jason R. Miller, “ Frequency Domain Characterization of Power Distribution Networks” Artech House Inc., 2007, PP , . 43-54. 8. “Mathcad 2001 User’s Guide” Math Soft Inc. 2001, P 286 , . 9. “Information technology – Serial Attached SCSI – 1.1 (SAS-1.1)” Work, ing Draft American National Standard, Project T10/1601-D, Revision 10, September 21, 2005, PP 136-146. . 10. Abe Riazi, “Timing Analysis Techniques for Digital PCBs, Printed ” Circuit Design & Fab, February 2008, PP 17-19. . B P O SE EX RIN OT E U PO TE H 1 S 3A LA D C 26 T S IR IP VE CU C G IT AS IMAGECURE SMART® A UNIQUE ADVANCED RESIN TECHNOLOGY Utilising a unique advanced resin technology developed by Sun Chemical, we are now able to offer a new SMART (SolderMask Advanced Resin Technology) product, which meets the industry needs of tomorrow, today. ImagecureSMART ® OFFERS: Halogen free Meets all current OEM specifications Lower temperature pre-dry window offering a significantly harder tack-free finish One product with increased photospeed allowing exposure by LDI or standard contact printingsystems One product for both Solvent and Aqueous developing Ability to hold fine lines and features Excellent resistance to all current final surface finishes including lead free solder Can be laser ablated for ease of traceability RoHs compliant Sun Chemical Circuits Norton Hill Midsomer Norton Bath BA3 4RT United Kingdom Tel: +44 (0) 1761 414 471 Fax: +44 (0) 1761 416 609 www.sunchemicalcircuits.com APRIL 2008 PRINTED CIRCUIT DESIGN & FAB 21 http://www.sunchemicalcircuits.com http://www.sunchemicalcircuits.com
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 - (Page Belly1) Printed Circuit Design & Fab - April 2008 - (Page Belly2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover1) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page 1) Printed Circuit Design & Fab - April 2008 - Contents (Page 2) Printed Circuit Design & Fab - April 2008 - Contents (Page 3) Printed Circuit Design & Fab - April 2008 - Our Line (Page 4) Printed Circuit Design & Fab - April 2008 - Our Line (Page 5) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 8) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 9) Printed Circuit Design & Fab - April 2008 - Around the World (Page 10) Printed Circuit Design & Fab - April 2008 - Around the World (Page 11) Printed Circuit Design & Fab - April 2008 - Around the World (Page 12) Printed Circuit Design & Fab - April 2008 - Around the World (Page 13) Printed Circuit Design & Fab - April 2008 - Happenings (Page 14) Printed Circuit Design & Fab - April 2008 - Happenings (Page 15) Printed Circuit Design & Fab - April 2008 - ROI (Page 16) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast1) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast2) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast3) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast4) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast5) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast6) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast7) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast8) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast9) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast10) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast11) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast12) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast13) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast14) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast15) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast16) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert1) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert2) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert3) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert4) Printed Circuit Design & Fab - April 2008 - ROI (Page 17) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 18) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 19) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 20) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 21) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 22) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 23) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 24) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 25) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 26) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 27) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 28) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 29) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 30) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 31) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 32) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 33) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 34) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 35) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 36) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 37) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 38) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 39) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 40) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 41) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 42) Printed Circuit Design & Fab - April 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - April 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover4)
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