Printed Circuit Design & Fab - April 2008 - (Page 22) Holewall Pullaway and Resin Recession Maintaining the electroless copper process chemistry within recommended range can alleviate many common plating problems. WE DEVOTED THE last several columns to voids and holewall pullaway. Before moving on to discuss other defects, this edition will discuss resin MICHAEL recession and finish CARANO with a case study on Holewall Pullaway (HWPA). While they are two unrelated issues – one is a defect and the other is not – both will receive appropriate discussion. Resin recession is primarily a material issue, not a plating/metallization defect. On casual inspection, resin recession can be, and often is, confused with HWPA. Resin shrinks during solder shock and other thermal excursions, and resin that is not completely cured will be more prone to shrinkage. An example of resin recession is shown in FIGURE 1, and holewall pullaway in FIGURE 2. One way to determine the difference is to look carefully at a cross-section. In Figure 1, the plated copper edge is very straight, and the resin is pulled back, indicating resin recession. In Figure 2, one can see that the plated copper vertical sidewall is “bowed outward.” The bowed copper is often seen as minor “blisters” or areas where the copper has lost adhesion. Resin recession is often seen with under cured laminate. To check the degree of cure, you can use thermal mechanical analysis or differential scanning calorimetry. Undercured material will shrink or recede during thermal excursions. Depending on the type of chemistry employed for desmear, certain material combinations can exaggerate the degree of resin recession. If the solvent used prior to permanganate is overly aggressive with respect to its penetration into the resin, recession will be evident. If using a 100% organic solvent for pre-conditioning, consider a different solvent system or one with a reduced concentration to minimize penetration. A PCB fabricator recently reported a an increase of sporadic holewall pullaway. The defect was exhibited in both small and large diameter vias in standard FR-4 material. Defects were seen on multilayer designs of 6 to 8 layers. For the past two years, a standard EDTA based electroless copper (medium deposition type) was employed. The process was designed to deposit 50 to 60 microinches of copper in 30 minutes. Solution operating temperature was specified to be 75 to 85˚F. The operators were interviewed and suggested “nothing had changed” in the process operation, yet visual inspection of some panels showed a noticeably darker color to the plated copper on some product. In addition, weight gain measurements yielded information that indicated that occasionally, deposits as high as 90 to 100 microinches of copper were recorded. Interestingly, the operators were not concerned with this discrepancy, but solder floating several coupons from these overplated boards showed a high level of HWPA. The main cause is quite simple – the electroless copper deposit was deposited in a stressed condition. Remember, this particular electroless copper process is formulated to deposit 50 to 60 microinches in 30 minutes, not 90 to 100 microinches in the same time period. Keep in mind that when the electroless copper process is operated outside of normal operating parameters, problems can happen. Now let’s get to the root cause of the problem. Often it’s in the details. The electroless copper solution was maintained with a single channel controller that monitored the copper content in the working solution. Based on the copper analysis, the other chemicals were replenished in the standard proportion required to maintain the process in the working range. This means that the sodium hydroxide content was added based on the copper that was required in the solution. Unfortunately, the sensor for the copper was not calibrated properly. Thus, the controller thought it was seeing a lower level of copper than what was really in solution. In reaction to the incorrectly measured, low copper levels, the controller called for the addition of copper and sodium hydroxide in amounts that where much higher than the electroless copper process needed. The higher than required levels of hydroxide drove the deposition rate beyond the designed 50 to 60 microinches, resulting in the stressed, heavy copper deposit. Remember, any process change that can lead to a greater than normal deposition rate can cause holewall pullaway. All chemistries should be operated and maintained according to the manufacturers’ recommendations. PCD&F MICHAEL CARANO is vice president for OM Group Inc. and can be reached at mike.carano@omgi.com. APRIL 2008 FIGURE 1. Resin recession. 22 FIGURE 2. Holewall pullaway (HWPA). PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 - (Page Belly1) Printed Circuit Design & Fab - April 2008 - (Page Belly2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover1) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page 1) Printed Circuit Design & Fab - April 2008 - Contents (Page 2) Printed Circuit Design & Fab - April 2008 - Contents (Page 3) Printed Circuit Design & Fab - April 2008 - Our Line (Page 4) Printed Circuit Design & Fab - April 2008 - Our Line (Page 5) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 8) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 9) Printed Circuit Design & Fab - April 2008 - Around the World (Page 10) Printed Circuit Design & Fab - April 2008 - Around the World (Page 11) Printed Circuit Design & Fab - April 2008 - Around the World (Page 12) Printed Circuit Design & Fab - April 2008 - Around the World (Page 13) Printed Circuit Design & Fab - April 2008 - Happenings (Page 14) Printed Circuit Design & Fab - April 2008 - Happenings (Page 15) Printed Circuit Design & Fab - April 2008 - ROI (Page 16) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast1) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast2) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast3) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast4) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast5) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast6) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast7) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast8) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast9) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast10) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast11) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast12) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast13) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast14) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast15) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast16) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert1) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert2) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert3) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert4) Printed Circuit Design & Fab - April 2008 - ROI (Page 17) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 18) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 19) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 20) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 21) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 22) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 23) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 24) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 25) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 26) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 27) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 28) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 29) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 30) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 31) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 32) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 33) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 34) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 35) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 36) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 37) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 38) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 39) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 40) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 41) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 42) Printed Circuit Design & Fab - April 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - April 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover4)
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