Printed Circuit Design & Fab - April 2008 - (Page 24)

DfM Improving FABRICATION YIELDS by Design The PCB designer is the architect for improved PCB yields. by ZULKI KHAN A major requirement in improving board fabrication yields is doing it right the first time, because once the PCB fabrication process is complete there is really no way to go back to fix major mistakes. In some cases you can mitigate design issues during the PCB assembly process, but during PCB fabrication, once layers are laminated and the holes are drilled, you cannot easily undo the process to make corrections. Therefore, to improve fabrication yields during and after design layout, it’s critical to follow the detailed fabrication notes and drawings, specifically calling out every item that requires any kind of explanation. This includes stack up data, layer construction information, material call outs, as well as drill charts specifying hole counts and symbols, whether drill holes are plated, and any similar information. Notes and drawings must not have sketchy or ambiguous information, nor should they lead the PCB fabricator to make “guesstimates” about some of the directions. Fabrication notes and drawings must have clear-cut and precise information in their instructions – assumptions are not allowed. If questions arise, the OEM customer should be consulted, and the OEM should resolve any uncertainties. A good rule of thumb is to engage the fabrication house during PCB layout/design stage. After the designer creates the stack up for impedance control, it’s a good idea to get it verified before the files are released to the fab house. Conversely, the fab house can play a reciprocal role by providing the designer with recommendations and suggestions for boosting yields. For example, a fab house may recommend material changes for a specific application that are better suited to increasing yields than those a designer specifies. Also, it is a good idea to check the capabilities of a fabrication house before releasing a job to them. If the PCB design calls out for 3 mil lines and spaces, and the fab house does not have the capability to generate this type of feature, they can inadvertently over or under etch traces, causing open or 24 shorts resulting in yield issues. Therefore, working together, the designer and fab house engineer can resolve any question, issue, or ambiguity that arises at an early stage in the design process, before the design ever reaches the fabrication floor. The Importance of Fabrication Drawing The PCB designer is the lynchpin for improving fabrication yields from the start. The fabrication drawing – the result of the PCB layout/design – is the tool they rely on to achieve this objective. A seasoned designer always finishes their layout by providing a complete fabrication drawing. An efficient fabrication drawing has four components – notes, mechanical dimensions/drawings, stack up callouts, and a drill chart seen in FIGURE 1. Fabrication notes include a wide range of technical details and instructions. The more complete and accurate they are, the more likely that the fabrication house will be able to produce the PCBs with requisite high yields. The following are some of the critical areas that should be covered in fab notes. It is important to list the IPC class (I, II, or III) on the fabrication notes. Also, the designer should specify the required board materials and surface finishes such as HASL (lead-free or tin-lead type), electroless nickel and immersion gold (ENIG), immersion silver or tin. If it’s gold, what is the quantity and type? A typical soldering applications might call for 3 to 5 microinches of gold over 150 to 200 microinches of nickel. A higher thickness and different type of gold would be needed for specialized applications such as wire bonding. The designer should also include, whenever possible, a note designating a secondary (equivalent) material and manufacturer name if the primary choice is not available at the fabrication house. It may take a week or more to acquire material, causing OEM product delivery delays. That’s the level of detail the designer must include in their notes. APRIL 2008 PRINTED CIRCUIT DESIGN & FAB

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Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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