Printed Circuit Design & Fab - April 2008 - (Page 26)

DfM eled (see FIGURE 3). The datum point 0,0 must be specified, so that every other dimension is measured from that original point. Cutouts, slots, and holes must also be meticulously designated. On the drawing, there are two sides for reference designators. At times, the designer might note a special feature on the bottom side that isn’t required on the top side. This distinction must be made in the fabrication drawing. If not, the fabrication house is left to make what perhaps can be a faulty assumption. Other details the designer must include would be any special features, like counter sink holes or sequential lamination. Stack up callouts specify board thickness, composition of internal layers, pre-preg thickness, and copper ounces per square inch used on the board. At the layout stage, the designer should perform precise calculations on the amount of current that will flow through the board. The callout specifies the thickness of copper (measured in ounces) to comply with current requirements. What must be avoided is the fabrication house relying on their own judgment, or making a decision using no calculations at all. (Note: an “inaccurate judgment” is not the fault of the fabricator, it’s a design error.) When calling out for impedance control requirements, a precise tolerance, such as 5% or 10% should be specified. For high-speed designs, impedance requirements could be single ended, or multiple differential impedances. Since there are many factors that can change the impedance on a board, a seasoned designer is always aware and mindful of these factors, which may include the stack up of the board, number of ground planes, trace width and thickness and the dielectric constant. Lastly, the drill chart covers four aspects – the symbols used, the size of the tools, the quantity of each drill size, and if holes are plated or non-plated. When defining drill symbols to distinguish multiple drill sizes used on the board, a separate precisely defined symbol should be used to make this distinction clear and without ambiguity. Accurate and comprehensive attention to detail should result in as near an ideal fabrication drawing as possible. A drawing of this caliber eliminates most or all of the uncertainty in the planning and computer-aided manufacturing (CAM) stages, as well as many that may be raised by the fabrication house. The CAM stage allows the fabrication house to review the different files generated in the PCB layout process. This includes Gerber files, which generates renderings that show layers, power and ground planes, drill holes, etc. At this point, oversights and potential problems can be corrected, as the efficient use of a sophisticated CAM tool will uncover discrepancies, such as half moons, stubs, or missing connections. Assumptions and Common Sense Wrong assumptions can cover many aspects of the PCB fabrication process that may include surface finishes, board material, copper plating, and other smaller details such as platedthrough holes (PTH) versus non-plated through holes. In the case of the PTH, it can create a short between the chassis and screw tightening the board, if specified incorrectly. At times, surface finish may not be specified by the OEM customer, and an assumption may be made to apply a HASL surface finish, but in a lead-free application, a silver or gold finish might be required to withstand the high thermal profile during reflow. Improving fabrication yields requires the designer to use plain old common sense, as well as applying their extensive experience and knowhow. A seasoned designer knows precisely where the pitfalls exist in a board design, and applies all the tricks and techniques they have learned from previous experience. A considerable amount of that design knowledge results from practical hands-on experience, rather than from textbooks or formal training. PCD&F ZULKI KHAN is president and founder, Nexlogic Technologies and can be reached at zk@nexlogic.com. 26 PRINTED CIRCUIT DESIGN & FAB APRIL 2008 http://www.chemcut.net http://www.chemcut.net

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Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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