Printed Circuit Design & Fab - April 2008 - (Page 28)

itance, or they can represent other physical quantities such as geometric length or dielectric constant. When the first simulation is run, these variable parameters are given user-defined seed values (Note 1 in Figure 1). When the first simulation iteration is complete, the circuit performance is compared to the desired results using a set of user-defined metrics (Note 2 in Figure 1). The metrics can be simple, involving single-point values such as a specified voltage at a circuit node, or they can consist of complex functions such as relative match of two waveforms over time. If the simulated performance falls within a specified tolerance of the desired performance, then the optimization routine is complete and returns the original seed values. If the simulated performance does not match the desired performance, then the internal optimization algorithm considers the previous results and calculates new values for the circuit’s variable parameters (Note 3 in Figure 1). Using the new values, the simulation is run again, the new simulated results are compared with the desired results, and the iterative process continues until the desired performance is obtained. The output of the process is the parametric values that allow the circuit performance to meet completion criteria. The advantage in using optimization routines comes from the algorithm that calculates new values for the circuit’s variable parameters. Typically, these routines can adjust many variables simultaneously with fast convergence to an optimal operating point. FIGURE 3. Waveforms at the four loads using conventional termination. Over the years, numerous algorithms have been developed4-10, and each has its own respective strengths and weaknesses, the detailed discussion of which is beyond the scope of this article. Challenge: Multi-Drop Bus Optimization routines can be of significant help in many unexpected ways, one of which is aiding in the development of application-specific termination schemes. To provide an example of such an application, this section describes the process of using optimization routines to solve a common design challenge – the desire to increase effective memory depth without increas- ing pin count or routing density – accomplished by sharing address and data busses between multiple memory chips. As shown in FIGURE 2, the associated net topology is called a multi-drop bus. Here, a single output buffer (often a processor ASIC) drives a trace with multiple stubs branching off the main trace with each stub having its own load device (memory chip). From an SI perspective, the challenges with this circuit topology include termination of each interconnect path, potential over-loading of the driver, and constructive/destructive interference from multiple reflections. A common termination approach for such a topology is simply to terminate the far end of the primary signal path with a 50-Ohm termination resistor to VTT. While such a termination scheme works well for simple point-to-point circuit topologies, the signal waveforms shown in FIGURE 3 clearly demonstrate the undesired effects of inappropriately using this design practice in a situation that requires more analysis. In this example based on 1.5-V HSTL signals, the signals collapse to levels within 90 mV of the 750-mV reference voltage, less than the 200-mV HSTL specification11 for AC conditions. Accordingly, the design needs to be changed for it to be reliably used in system applications. The difficulty here is in trying to determine what alternative circuit topologies to APRIL 2008 28 PRINTED CIRCUIT DESIGN & FAB http://www.pcb-pool.com/ppus/info.html?PHPSESSID=7df48fa7c977776045ff8d4b24a70fc7 http://www.free-pcb-software.com http://www.pcb-pool.com/ppus/info.html?PHPSESSID=7df48fa7c977776045ff8d4b24a70fc7

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Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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