Printed Circuit Design & Fab - April 2008 - (Page 29)

SI OPTIMIZATION FIGURE 4. “Kitchen sink” of termination options. FIGURE 5. Revised termination after removal of unnecessary series and shunt resistors. consider, and to then determine the appropriate values for each circuit element. To obtain adequate SI performance in a multi-drop net such as this, there are numerous termination options whereby termination resistors are placed in shunt and/or series at various circuit nodes. However, the proper location and value of the termination resistors is not readily apparent, and it would take significant time and effort to manually explore all possible options. Alternatively, we can use optimization routines to aid in determining proper termination architecture and associated resistor values. The process starts by tossing a veritable “kitchen sink” of termination options at the problem, as shown in FIGURE 4, where termination resistors are placed at each and every node, in both shunt and series configurations. The process then uses optimization routines on the “kitchen sink” circuit, and the resulting parasitic values are inspected. If any parasitic value falls outside a useful range, the entire element is removed from the circuit, and optimization is performed again. The process continues until all parasitic values approach reasonable and practical values and the resulting signal integrity is adequate. One common feature most optimization routines share is a decreased efficiency with an increase in the number of variables. If all twelve resistors and all seven line impedances in the above example were allowed to vary independently, the optimization process would take considerable time and the results could be impractical to implement. Alternatively, it is reasonable to constrain the primary path from the driver to the last receiver to one common line impedance, while all the stubs rely on different impedances. Similarly, the three resistors at each transmission line split can be chosen to be the same value as those on the other splits, thus further reducing the number of variables. With most optimization routines, seed and limit values are needed. For the transmission lines, a 50-Ohm impedance is most-often used and will be the suggested nominal value for the simulations. For the limits, practical values are chosen to range from 25 Ohm to 100 Ohm. For the shunt resistors, nominal 50 Ohm values are chosen with limits of 1 Ohm and 1,000 Ohm. For the series resistors, 10 Ohm nominal, 1 Ohm minimum, and 1000 Ohm maximum values are chosen. For all resistors, values approaching 1 Ohm will be considered shorts and values approach 1,000 Ohm will be considered opens. In all, the “Ventec laminate has been a tremendous asset in Titan PCB East’s ability to provide a high quality, high reliability lead free product to today’s time critical, cost sensitive market. Ventec VT-47 provides superior peel strength, high Td, Z-axis stability, thermal reliability, surface quality and inventory selection all in the same package. The fact that this is provided in a cost competitive manner is icing on the cake. Ventec is not just a player in the game, they are a top performer. The addition of VT-90 polyimide materials to the FR-4 offerings make Ventec a force to be reckoned with in the future.” Mike Berg, President and CEO, Titan PCB East – Amesbury, MA “When using the VT-47 and VT-481 materials, we have found above average drill and scoring characteristics without experiencing the fracturing and haloing associated with other well-known lead free comparable phenolic resin systems.” John Gratton Engineering Manager Century Circuits – Toronto, ON “We have been very pleased with the quality, service, performance, and consistency of the Ventec materials for almost two years now. I would not hesitate to recommend Ventec VT-47 to our customers as a reasonably priced alternative for lead free assembly.” Robert E. Welch Process Engineering Manager Waytec Electronics Corp. – Lynchburg, VA “The family of Ventec laminates has made an improvement in our processing of multilayer circuits. The materials exhibit very good consistency. Our quality department is very satisfied with the performance of these laminates.” Jim King Process Engineer Philway Products – Ashland, OH See us at IPC Expo Booth #919 Global Laminates Inc. 16 Hunt Rd. South • Amesbury, MA 01913 • (978) 388-9610 • (978) 388-5339 fax • www.globallaminates.com Sales reps and distributors wanted: email Bruce at bhurley@globallaminates.com APRIL 2008 PRINTED CIRCUIT DESIGN & FAB 29 http://www.globallaminates.com http://www.globallaminates.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - April 2008

Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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