Printed Circuit Design & Fab - April 2008 - (Page 37) TABLE 1. Example of the effect of liquid resist thickness on innerlayer yield. RESIST COATING THICKNESS (MICRONS) 8–9 10 – 11 NUMBER OF LAYERS EVALUATED 160 400 PANELS WITH OPENS OR NICKS 27 8 OPEN/NICK RATE (%) 17 2 Resist Development The developer process is required to remove unexposed resist (for a negative resist) so as to allow an accurate transfer of the image from the artwork to the final etched panel. Residual resist left in areas that were intended to be completely cleared will prevent the subsequent etch step from properly removing copper from those locations. Issues of this type may be associated with deficiencies in control of developer concentration or temperature, failure to ensure that horizontal equipment is properly maintained, for example, blocked spray nozzles or contamination of transport rollers. Even if the developer chemistry and equipment is properly maintained, inadequate time, temperature, water cleanliness or spray pressure in the post-develop rinse step may also lead to residuals being left on the panel surface. Optimum developer speed is established using breakpoint testing, where breakpoint is defined as the point at which the unexposed resist is first washed correlating the surface condition (using a combination of SEM and profilometry) with the data for resist adhesion after multiple passes through the subsequent development process. Liquid Resist Coating and Drying Maintaining the cleanliness of the environment used for the coating and drying steps is critical. When troubleshooting yield loss, examination of the resist layer after coating and drying can provide information on the nature and source of particulate contaminants. While 10 +/- 2 µm is often described as being the desired coating thickness range for liquid resists – depending on the process control and technology complexity level for an individual customer – the use of 8 to 9 µm coatings may not always provide acceptable yield. Using this approach to obtain initial baseline data for process capability, and updating that information when a higher difficulty product is introduced, will ensure that the best balance of performance and cost is achieved. Over or under drying a liquid resist can lead to a variety of issues. Under drying may lead to defects associated with damage during handling and stacking, loss of resist adhesion, and changes in resist exposure and development properties (such as excessive photospeed or formation of a negative or positive resist foot). In contrast, overdrying can lead to loss of photospeed and difficulty in achieving proper development. Sublimation of resist components can also be an issue if drying is too severe, leading to issues of debris build-up within the equipment. YOU’RE With 35 years of experience Resist Exposure Although collimated sources (in which the light radiation from the source follows a parallel path) may be used, non-collimated equipment is the norm for liquid resist exposure. The combination of higher exposure sensitivity of liquid resists with a collimated exposure source leads to an increased sensitivity to particulate contamination, with increased open/nick defects and lowered yields. Therefore the use of non-collimated light is much preferred. The equipment used must be capable of delivering sufficient light energy in an exposure duration that results in an acceptable production throughput. Enough exposure energy must be provided to allow the resist to be fully crosslinked, but excess energy will lead to lateral growth of the exposed area, with a consequent loss of resist line width control. Optimum exposure energy for a particular resist may be identified using a Stouffer Step tablet1. Since the artwork must be tightly held against the resistcoated substrate, insufficient delay time between vacuum application and exposure can adversely affect resolution. To confirm proper settings, evaluate resolution as a function of vacuum delay time. Artwork damage and contamination is also an ever-present concern. Repeating defects appearing at the same location on a panel is an indication of this issue. APRIL 2008 We make our own laminates in the U.S. • Material types in FR-4 Difunctional, Tetrafunctional and Multifunctional • Temperature ratings from 130˚C to 177˚C • Thickness ranges from .0025” to 3.000” • Coppers from 1/2 oz. to 6 oz. in stock • Black, Blue, Tan, Green, Orange & Natural • True Cryogenic G10 • Sheet sizes in 36”x48” • RoHS compliant, UL recognized and IPC approved Same Day Pricing and Lead Times Current, Inc. 30 Tyler St. Ext • East Haven, CT 06512 1-877-436-6542 • Fax 203-467-8435 www.currentcomposites.com Louis S. Owen, Director of Outside Sales 860-350-9607 • Fax 860-210-1748 PRINTED CIRCUIT DESIGN & FAB 37 http://www.photoplot.com http://www.currentcomposites.com http://www.currentcomposites.com
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - April 2008 Printed Circuit Design & Fab - April 2008 - (Page Belly1) Printed Circuit Design & Fab - April 2008 - (Page Belly2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover1) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page Cover2) Printed Circuit Design & Fab - April 2008 - Printed Circuit Design & Fab - April 2008 (Page 1) Printed Circuit Design & Fab - April 2008 - Contents (Page 2) Printed Circuit Design & Fab - April 2008 - Contents (Page 3) Printed Circuit Design & Fab - April 2008 - Our Line (Page 4) Printed Circuit Design & Fab - April 2008 - Our Line (Page 5) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 8) Printed Circuit Design & Fab - April 2008 - Market Watch (Page 9) Printed Circuit Design & Fab - April 2008 - Around the World (Page 10) Printed Circuit Design & Fab - April 2008 - Around the World (Page 11) Printed Circuit Design & Fab - April 2008 - Around the World (Page 12) Printed Circuit Design & Fab - April 2008 - Around the World (Page 13) Printed Circuit Design & Fab - April 2008 - Happenings (Page 14) Printed Circuit Design & Fab - April 2008 - Happenings (Page 15) Printed Circuit Design & Fab - April 2008 - ROI (Page 16) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast1) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast2) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast3) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast4) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast5) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast6) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast7) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast8) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast9) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast10) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast11) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast12) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast13) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast14) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast15) Printed Circuit Design & Fab - April 2008 - ROI (Page PCBEast16) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert1) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert2) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert3) Printed Circuit Design & Fab - April 2008 - ROI (Page Insert4) Printed Circuit Design & Fab - April 2008 - ROI (Page 17) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 18) Printed Circuit Design & Fab - April 2008 - Tip Jar (Page 19) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 20) Printed Circuit Design & Fab - April 2008 - Interconnect Strategies (Page 21) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 22) Printed Circuit Design & Fab - April 2008 - Positive Plating (Page 23) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 24) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 25) Printed Circuit Design & Fab - April 2008 - Improving Fabrication Yields by Design (Page 26) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 27) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 28) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 29) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 30) Printed Circuit Design & Fab - April 2008 - Solve Design Problems with Signal Integrity Optimization (Page 31) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 32) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 33) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 34) Printed Circuit Design & Fab - April 2008 - Laser Direct Imaging Made Easy (Page 35) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 36) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 37) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 38) Printed Circuit Design & Fab - April 2008 - Troubleshooting the Innerlayer Process (Page 39) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 40) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 41) Printed Circuit Design & Fab - April 2008 - SIPS Give More to Moore (Page 42) Printed Circuit Design & Fab - April 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - April 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - April 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - April 2008 - BGA Bulletin (Page Cover4)
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