Printed Circuit Design & Fab - April 2008 - (Page 40)

PACKAGING DEVELOPMENTS SIPs Give More to Moore SiP-based system-level integration resolves CMOS scaling limits. by DR. W.R. BOTTOMS The electronics industry is nearing the limits of traditional CMOS scaling. Although predictions that Moore’s Law has reached its limits have been heard for years, they have proved premature. We are now, however, nearing the basic physical limits to CMOS scaling, and the price elastic growth of the industry can no longer continue based solely on Moore’s Law scaling. New materials and device architectures in development will eventually provide a path to increased density, increased performance and lower cost beyond the capability of CMOS-based circuits. However, there will be a time lapse between the slowing Λ . . . 22 nm 32 nm 45 nm 65 nm 90 nm Information Processing Digital content System-on-Chip (SOC) 130 nm of traditional CMOS scaling and the rollout of architectures and materials that can support Moore’s Law scaling. In the meantime, as scaling become more difficult, packaging innovations are taking up the slack (FIGURE 1). The International Technology Roadmap for Semiconductors (ITRS) defines functional diversification, incorporating system-level functions into a single package, as “more than Moore.” This approach enables continued rapid progress in functional density during a period where traditional CMOS scaling cannot keep the pace and new architectures are not yet ready. A second key Beyond CMOS Baseline CMOS: CPU, Memory, Logic Analog/RF Passives HV Power Sensors Actuators Biochips More than Moore : Functional Diversification Interacting with people and environment Non-digital content Systemin-Package (SiP) FIGURE 1. SoC and SiP technologies provide a path for continued improvement in performance, power, cost and size at the system level, exclusive of conventional CMOS scaling. 40 contribution of packaging to maintaining the pace of functional density scaling is 3-D integration. Both these innovations are accomplished through integration of multiple circuit types into a single device using system-onchip (SoC) and system-in-package (SiP) technologies. As electronics becomes more consumer-dominated, the most important of these will be SiP. ITRS defines SiP as “a combination of multiple active electronic components of different functionality, assembled in a single unit that provides multiple functions associated with a system or subsystem. SiPs may optionally contain passives, MEMS, optical components and other packages and devices.” SiP technology enables the efficient use of three dimensions through innovation in packaging and interconnect. The result supports continued increased functional density and decreased cost per function. Although there will be some applications where SoC represents the better alternative, SiP provides advantages over SoC in most market segments. The importance of these advantages varies with different applications. They include: ■ Small and custom form factors. ■ Decreased weight. ■ Reduced power consumption. ■ High functional density. ■ High frequency operation. ■ Large memory capacity. ■ High reliability. APRIL 2008 PRINTED CIRCUIT DESIGN & FAB More Moore : Scalingn

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Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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