Printed Circuit Design & Fab - April 2008 - (Page 41)

FIGURE 2. Innovation in SiP architectures. FIGURE 3. 3-D packaging technology today. Simplest WLCSP structure WLCSP with Cu post and resin mold Low package cost. Lower development cost, greater integration flexibility, lower NRE cost and lower product cost compared to SoC. ■ Rapid time to market. ■ Wireless connectivity (GPS, Bluetooth, cellular, etc.). SiP is not a replacement for the high-level, single-chip, silicon integration of SoC. It is complementary, and some complex SiP products will contain SoC components. SiP technology is evolving from a specialty used in a narrow set of applications, to a high-volume technology with wide-ranging impact on electronics. The broadest adoption of SiP to date has been for stacked memory/logic devices and small modules used to integrate mixed-signal devices and passives. Both these applications are driving high volume in very cost-competitive markets. SiP has rapidly penetrated many market segments, including consumer electronics, mobile devices, automotive controls and sensors, computing, networking, communications and medical electronics. SiP’s benefits vary by market segment but share some elements. Time-to-market, size, power requirements and cost have resulted in SiP’s strongest initial penetration: mobile communications. Unit shipments have been rising at approximately 25% per year, and this growth is forecast to continue. ■ ■ Embedded device in polymer dielectric Opto WLCSP with Beam Lead IPD embedded silicon substrate High capacity memory processor Stacked devices with TSV Build-up substrate through wafer level fabrication Embedded wafer level package FIGURE 4. Examples of wafer-level packaging innovations. Challenges for SiP Traditional single-chip packaging and system-level interconnect have limitations in interconnect density, thermal management, bandwidth and signal integrity that can be met only with new approaches. SiP technology is the most important new technology to address these limitations. Nonetheless, there are still a number of challenges, the most critical of which are: ■ Interconnection capable of maintaining power integrity for actives. ■ Performance and reliability of electronic systems are limited by the ability of on-chip and off-chip system-level interconnections to maintain power integrity during operation. ■ Interconnect inductance, high current requirements, increasing frequency and decreasing operating voltage all increase the difficulty. SiP technology enables improvement in each of these parameters, but challenges must be addressed if SiP is to meet its potential. Thermal dissipation. Inadequate thermal dissipation imposes the most serious bottleneck to SiP performance. Not only does the thermal dissipation technology dictate the chip APRIL 2008 junction temperature and subsequently its performance, but the thermal technology’s size and cost will limit packaging density, size and cost of SiP-based products. Thermal dissipation is also the key limiter to 3-D stacking of microprocessors and other high power/density ICs. Signal bandwidth. Even though bandwidth is often better than for single-chip packages, inadequate chip I/O bandwidth is the third serious challenge to the realization of ultimate performance. Losses resulting from package substrate properties, crosstalk and impedance mismatches are exacerbated as off-chip bandwidth per channel increases and signal noise budgets decrease. Perhaps the greatest issue is the inability of the small transistor to drive off chip impedance at high speed. SiP technologies address these limitations and offer major improvements, but much development work remains. SiP Evolution SiP technology builds from the state-of-the-art in single-chip packaging, with its advanced wirebond and flip-chip processes, by integrating new technologies to support system-level integration. Emerging technologies that will be combined with this base include wafer-level packaging, die stacking, package stacking, through-silicon vias (TSV), 3-D packaging, printable circuits, thinned wafers, and embedded actives and passives. The current technical solutions for 3-D packaging include wire bonding, face-to-face bonding and multilayer TSV structures (FIGURE 3). PRINTED CIRCUIT DESIGN & FAB 41

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Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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