Printed Circuit Design & Fab - April 2008 - (Page PCBEast9)

PROFESSIONAL DEVELOPMENT effects on the schematic, EMI, board stackup, fabrication, testability, repair and assembly. It will also cover a typical design flow, routing plans, routing for best signal integrity, what’s most important when routing, signals of greatest concern, I/O structures, differential pairs, analog vs. digital, and much more. NEW! T7 - DFM: A Foundation for Cost-Reduction Efforts Speaker: Gary Ferrari, FTG Circuits Lead free, small-pitch BGAs, microvias, embedded passives, controlled impedance, EMI…what next? Each of these technologies presents manufacturing challenges that must be addressed by both today’s designer, as well as any cost-reduction team. We find it easy to blame escalating costs on these new technologies. However, much of the blame may be attributed to a lack of understanding of the manufacturability rules associated with these technologies. As a designer, we should be designing for the most cost-effective product without sacrificing performance. Cost reduction, by design, forms the fundamental building blocks for this session. This full-day tutorial will be divided between lectures and interactive discussion groups. The discussion groups will explore, under guidance, material issues for lead and lead-free environments, high performance, HDI, assembly, and surface finishes for various environments. The tutorial also will look at the impact of demands placed on our industry by a growing number of lead-free directives on fabrication and assembly processes. Finally, the groups will discuss new and innovative ways to test and verify a product’s integrity in both current and lead-free products. T8 - BGA Challenges Speaker: Charles Pfeil, Mentor Graphics PCBs with multiple large BGAs present a significant routing challenge, often resulting in an excessive number of layers and compromises on signal integrity. This workshop explores stackups, via models, fanout patterns and routing techniques that will enable fewer layers and reduced costs while maintaining signal integrity. 3-Day Technical Conference Program The 3-Day Technical Conference consists of 33 two-hour workshops (W courses) and half-day seminars (S courses) on Monday, May 12, Wednesday, May 14 and Thursday, May 15. Tuesday, May 13 is “FREE Tuesday,” a special day that provides attendees with a variety of complimentary special events and sessions, and plenty of time to visit the exhibition. The short technical courses that make up the 3-Day Techical Conference are included on the Proceedings CD-ROM provided to all conference attendees. MON MAY 12 | 9 AM – 11 AM NEW! W3 - Base Materials for High-Speed, HighFrequency and Lead- Free PCBS Speaker: Rick Hartley, L-3 Communications, Avionics Systems In a high-speed or high-frequency circuit, performance is dependent upon a number of characteristics and variables, which all accumulate to affect the noise budget of the circuit. Several of these issues are driven by the PCB’s base material characteristics. At high frequencies, materials can and do have a profound impact on performance. This two-hour workshop will discuss the base materials commonly used in high-speed digital and high-frequency analog circuits (including FR4), looking at their advantages and disadvantages. It will also detail how to calculate their impact on circuit performance, hence how to choose a cost-effective material for any specific application. Finally, the workshop also will look at how each of these materials fits into today’s lead-free products. W1 - Catch & Release: Verifying, Optimizing, Post Processing and Documenting PCB Designs for Manufacturing Speakers: Rick Almeida and Fay Fugitt, DownStream Technologies This two-hour workshop will focus on expediting the post processing of PCBs—including verifying manufacturing data, optimizing output creation and automating documentation—to generate one electronic file that contains all information to fabricate and assemble PCBs anywhere and at anytime. NEW! be set up and what attributes and information might be included. We will talk about the reasoning behind the conventions used for building parts and how they apply to others in engineering and manufacturing. Additionally, we will discuss ideas for checking footprints, and naming and saving conventions. NEW! S3 - Design For Flip-Chip, Chip-Size and 3-D Array Package Technology Speaker: Vern Solberg, consultant The gap between PCBs and semiconductor technology (wafer-level integration) is greater than one order of magnitude in interconnection density capability, although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process. This half-day seminar provides a comparison of different commonly used technologies including flip-chip, chip-size, wafer-level and 3-D array package methodologies detailed in a new publication, IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format and the impact on current component characteristics, and reviews the appropriate PCB design guidelines to ensure efficient assembly processing. W2 - Design Principles for BGA, CSP and 3D Package Technologies Speaker: Vern Solberg, consultant Many of the new miniature IC device families have more contacts and a finer contact pitch than their predecessors, dramatically affecting the methodology used in board design and assembly. Because of the higher component density made possible by adapting these newer generations of IC package technologies, assembly specialists have found that an optimized design layout, land pattern geometry refinement and the selection of quality substrate materials can have a positive affect on both manufacturing efficiency and product reliability. This two-hour workshop will address these design principles by focusing on the latest version of the IPC-7094 and IPC-7095 documents covering both wide and finepitch BGA packaging methodology. Topics of discussion will include: BGA package selection criteria; applicable standards for BGAs and CSPs; BGA package assembly variations; land pattern design and high-density circuit routing; PCB material selection and fabrication options; and design for assembly automation. The workshop also will discuss IC packaging standards, review qualification requirements, and study alternative land pattern geometries and circuit routing guidelines, as well as important factors related to high-density PCB fabrication technologies, assembly process development, inspection criteria and solder quality assessment. MON MAY 12 | 9AM – 12:30 PM S1 - Resources and Standards for Your Company Speaker: Susy Webb, Fairfield Industries This half-day seminar will provide attendees with an extensive list of Web sites, calculators, software and ideas that designers of any level can use to increase their own productivity. We will first discuss standards and suggest plans for what should be standardized within your company and how to go about setting that up. We also will discuss ideas for organizing the input, output and checking procedures; naming and saving conventions; and working with specifications and reference materials. Finally, we will go through a large accumulation of resources that are set up for designers to use to enhance their knowledge and abilities. S4 - Embedded Passive Component Technology Available Now Speaker: Richard Snogren, Bristlecone This half-day seminar is a review of the state-of-theart as it applies to today’s commercially available embedded passive component materials technology. The course starts with passive component functions and performance drivers to embed passives. This leads into an in-depth discussion of today’s commercial material sets; their electrical and physical characteristics; a useable selection rationale; design, test, and trim tools; and DFM guidelines for implementation. The presentation includes discussion of the relative costs of the various technologies and a methodology for cost analysis. and concludes with a review of industry initiatives on embedded passive components. MON MAY 12 | 1:30 PM – 5 PM NEW S2 - Library Creation and Management Speaker: Susy Webb, Fairfield Industries Library creation is the cornerstone of good design work. If parts and symbols are not consistent and accurate, time may be required for editing when it would be better spent getting the project out on schedule. This half-day seminar will discuss the creation of schematic and PCB libraries, and suggest ideas for how they might EARLY-BIRD DISCOUNT DEADLINE | REGISTER BY APRIL 10 AND SAVE UP TO $100!

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - April 2008

Printed Circuit Design & Fab - April 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Positive Plating Improving Fabrication Yields by Design Solve Design Problems with Signal Integrity Optimization Laser Direct Imaging Made Easy Troubleshooting the Innerlayer Process SIPS Give More to Moore Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - April 2008

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