Printed Circuit Design & Fab - May 2008 - (Page 20) SIGNAL INTEGRITY Don’t Let Your Signals STUB THEIR TOES Via stubs can be tamed by keeping the length short, restricting signal layer transitions, and utilizing back drilling in multigigabit applications. by DR. ERIC BOGATIN You need to read this article because you’ve built your backplane with the lowest dielectric loss laminate you could afford. The connectors are rated at 20 GHz bandwidth, and your trace impedances are within 5% of 100 Ohms. Your SERDES I/O drivers have multi-tap de-emphasis and equalization built in. All 50 inches of path length is perfectly matched and tuned. You’ve simulated the system with a pretty good link analyzer and have confidence you will see a 10 Gbps eye that is open with plenty of margin over the eye mask. But, when you power on and look at the eye for the first time, it’s nearly closed. The bit error rate (BER) is 0.1%, more than nine orders of mag- nitude higher than you expected! So, what went wrong? What’s killing the signal? Like a tiny clot in an artery that can take a person down, one of the killers of high speed serial links is the via stub, a tiny piece of interconnect, that can take down a backplane many times its size. It is an artifact of the process of manufacturing through hole vias, and can be the death of a high speed interconnect. Through Hole Vias Vias are essential structures in all multilayer circuit boards that enable a signal to switch from one layer to another. The through hole via – often referred to as a plated through hole (PTH) via – is by far the most common and the lowest cost via in multi layer boards. After the entire board is laminated in a press, vias are mechanically drilled through the entire stack, and the inside of the hole (called the barrel) is metallized to make it conductive using an electrochemical plating process. Surface traces and pads are plated at the same time. Every through hole is capable of connecting any layer to any other layer. Each through hole is programmed by the pads, signal lines or planes that intersect the drilled hole. When a drill passes through copper on any layer, the edge of the copper inside the hole is exposed, and when the entire barrel is metallized, any exposed metal is electrically connected. In a multilayer board, a via may connect a signal from any layer to any other layer. In the case of the 12-layer board shown in FIGURE 1, the via connects signal layers 1 to 4. As part of the manufacturing process, the via is plated all the way through the board, even though the signal itself may only travel through part of the barrel. The rest of the barrel (in this case, below layer 4) is called the stub. The residual stub acts as a short transmission line to the signal. At low frequency, the impact is a capacitive load, but at high frequency, it is a resonant structure that can have a dramatic impact on signal integrity. Electrical Performance of Vias The only way to know the precise electrical performance of the stub is by either simulating the via performance using a full wave electromagnetic simulation tool, or building a test structure and measuring it. FIGURE 2 shows the measured insertion loss of a long backplane trace MAY 2008 FIGURE 1. 3D model of two signal traces transitioning from layer 1 to layer 4, leaving a residual stub extending to the bottom of the board. Note the adjacent return vias, always a good design practice. 20 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - May 2008 Printed Circuit Design & Fab - May 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC For the Real World PCB East Conference Brochure Positive Plating Don't Let your Signals Stub Their Toes Improve PCB Layout With Skill Utility Programs The Next Generation Design Tool Challenge Thermally Conductive Microwave Materials PCB Dielectric Degradation in Lead-Free Assembly Applications A Tale of Two Trade Shows Eliminating Board Defects Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - May 2008 Printed Circuit Design & Fab - May 2008 - Printed Circuit Design & Fab - May 2008 (Page Cover1) Printed Circuit Design & Fab - May 2008 - Printed Circuit Design & Fab - May 2008 (Page Cover2) Printed Circuit Design & Fab - May 2008 - Printed Circuit Design & Fab - May 2008 (Page 1) Printed Circuit Design & Fab - May 2008 - Contents (Page 2) Printed Circuit Design & Fab - May 2008 - Contents (Page 3) Printed Circuit Design & Fab - May 2008 - Our Line (Page 4) Printed Circuit Design & Fab - May 2008 - Our Line (Page 5) Printed Circuit Design & Fab - May 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - May 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - May 2008 - Around the World (Page 8) Printed Circuit Design & Fab - May 2008 - Around the World (Page 9) Printed Circuit Design & Fab - May 2008 - Around the World (Page 10) Printed Circuit Design & Fab - May 2008 - Around the World (Page 11) Printed Circuit Design & Fab - May 2008 - Happenings (Page 12) Printed Circuit Design & Fab - May 2008 - Happenings (Page 13) Printed Circuit Design & Fab - May 2008 - ROI (Page 14) Printed Circuit Design & Fab - May 2008 - ROI (Page 15) Printed Circuit Design & Fab - May 2008 - EMC For the Real World (Page 16) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-1) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-2) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-3) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-4) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-5) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-6) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-7) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-8) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-9) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-10) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-11) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-12) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-13) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-14) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-15) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-16) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page 17) Printed Circuit Design & Fab - May 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - May 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 20) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 21) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 22) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 23) Printed Circuit Design & Fab - May 2008 - Improve PCB Layout With Skill Utility Programs (Page 24) Printed Circuit Design & Fab - May 2008 - Improve PCB Layout With Skill Utility Programs (Page 25) Printed Circuit Design & Fab - May 2008 - The Next Generation Design Tool Challenge (Page 26) Printed Circuit Design & Fab - May 2008 - The Next Generation Design Tool Challenge (Page 27) Printed Circuit Design & Fab - May 2008 - The Next Generation Design Tool Challenge (Page 28) Printed Circuit Design & Fab - May 2008 - Thermally Conductive Microwave Materials (Page 29) Printed Circuit Design & Fab - May 2008 - Thermally Conductive Microwave Materials (Page 30) Printed Circuit Design & Fab - May 2008 - Thermally Conductive Microwave Materials (Page 31) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 32) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 33) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 34) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 35) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 36) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 37) Printed Circuit Design & Fab - May 2008 - A Tale of Two Trade Shows (Page 38) Printed Circuit Design & Fab - May 2008 - A Tale of Two Trade Shows (Page 39) Printed Circuit Design & Fab - May 2008 - Eliminating Board Defects (Page 40) Printed Circuit Design & Fab - May 2008 - Eliminating Board Defects (Page 41) Printed Circuit Design & Fab - May 2008 - Eliminating Board Defects (Page 42) Printed Circuit Design & Fab - May 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - May 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - May 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - May 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - May 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - May 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - May 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - May 2008 - BGA Bulletin (Page Cover4)
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