Printed Circuit Design & Fab - May 2008 - (Page 23)

SIGNAL INTEGRITY A slight amendment to this design guideline might be to limit any high-speed signal transitions from near a top layer to near a bottom layer. This will limit the length of a via from the surface to the lowest signal layer. For example, never route a signal from layer 1 to layer 4, but you can route a signal from layers 1 through 4 to layers 10 through 14. If you can’t make a via stub shorter, then the next knob to tweak is to increase their impedance by decreasing their capacitance. This can be accomplished by: ■ Use as narrow a barrel diameter as possible ■ Minimize the size of capture pads on the top and bottom surfaces ■ Remove all non functional pads on all intermediate layers ■ Increase the clearance holes through all planes as much as possible Every decrease in capacitance will help reduce the impact of the via stub. How do you know if it is enough? Use a full wave 3D field solver to simulate the via and its stub, or build a candidate via in a test coupon and measure it. Back drilling has become a conventional process that most fab shops routinely do with only a small price premium. The through hole via is manufactured in the conventional way, and then a drill bit with a diameter a few mils larger than the barrel is used to drill out the stub from one side of the board. This requires controlled depth drilling, which can typically be controlled to within 5-10 mils. Using back drilling, residual via stubs can easily be kept to less than 20 mils, which enables good signal quality for even 15 Gbps signals. Many backplanes have demonstrated more than 10 Gbps operation with conventional FR-4, preemphasis and equalization and with back drilled vias. Conclusions A tiny via stub, less than 150 mils long, can affect the performance of a high-speed serial link much more than an entire 50 inch long interconnect. The stub can be tamed by keeping its length short. Using the combination of careful design guidelines in the physical design of a via and restricting signal layer transitions, along with technology options such as back drilled vias, a high-speed designer should not hesitate to incorporate vias in multigigabit designs. PCD&F Back Drilling Stubs Sometimes it is not possible to restrict the layer transitions, and no matter how low you get the capacitance, you still have a stub and the impact of its resonance. You might still be able to eliminate the via stub by using blind or buried vias. An alternative is to back drill the via stub to remove the conductive barrel. DR. ERIC BOGATIN is president of Bogatin Enterprises LLC; eric@bethesignal.com. IMAGECURE SMART® Utilising a unique advanced resin technology developed by Sun Chemical, we are now able to offer a new SMART (SolderMask Advanced Resin Technology) product, which meets the industry needs of tomorrow, today. ImagecureSMART ® OFFERS: Halogen free Meets all current OEM specifications Lower temperature pre-dry window offering a significantly harder tack-free finish One product with increased photospeed allowing exposure by LDI or standard contact printingsystems One product for both Solvent and Aqueous developing Ability to hold fine lines and features Excellent resistance to all current final surface finishes including lead free solder Can be laser ablated for ease of traceability RoHs compliant A UNIQUE ADVANCED RESIN TECHNOLOGY Sun Chemical Circuits Norton Hill Midsomer Norton Bath BA3 4RT United Kingdom Tel: +44 (0) 1761 414 471 Fax: +44 (0) 1761 416 609 www.sunchemicalcircuits.com MAY 2008 PRINTED CIRCUIT DESIGN & FAB 23 http://www.sunchemicalcircuits.com http://www.sunchemicalcircuits.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - May 2008

Printed Circuit Design & Fab - May 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC For the Real World PCB East Conference Brochure Positive Plating Don't Let your Signals Stub Their Toes Improve PCB Layout With Skill Utility Programs The Next Generation Design Tool Challenge Thermally Conductive Microwave Materials PCB Dielectric Degradation in Lead-Free Assembly Applications A Tale of Two Trade Shows Eliminating Board Defects Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - May 2008

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