Printed Circuit Design & Fab - May 2008 - (Page 25)

the layout design of both PCBs. PCB A PCB B BEFORE AFTER CUSTOMIZATION CUSTOMIZATION Project Date # Pins Silk & Assembly (# hours) Silk & Assembly (# hours for 1K pins) Manufacturing (# hours) Manufacturing (# hours for 1K pins) Total (SA + Mfg) (# hours for 1K pins) Total (SA + Mfg) (# hours for 10K pins) TOTAL BENEFIT March 2006 9,438 32 3.4 17 1.8 5.2 (3.4 + 1.8) 52 290% April 2007 10,728 6.6 0.61 12.75 1.18 1.79 (0.61 + 1.18) 17.9 PCB layout hours for 10K pins project TABLE 1. Comparison table of work hours invested in 60 50 40 30 20 10 0 A A A B SA Mfg B Total B Total Benefit 290% PCB A - Before Customization PCB B - After Customization FIGURE 1. Number of hours invested in SA and MFG phases for a layout project with 10,000 pins. Gerber files at the click of a button, based on the layer order defined by the designers. Designers have a dynamic graphic interface available that displays the internal and external layers of the board, enabling them to select the relevant layers for creating the Gerber files. This application saves 98% of the time required to create Gerber files at the end of the design phase, and prevents potential errors in the manufacturing of the PCB. Check Padstacks is a service application that verifies the accuracy of the values of each pin in the PCB, as compared with values in accordance with IPC-7351 and IPC-2221/2. Recommended golden values in these standards constitute the database for the service application. Values checked include pad size, paste mask, solder mask, thermal relief and more. The application was written in Skill, with data processing in Perl. It prevents potential errors when defining footprints and ensures that the PCB will be produced and assembled quickly and smoothly, with zero faults in the determination of the components library. A block is defined as a group of components that repeat themselves. Copy Block is used to place identical blocks on the PCB and to correctly place components on each block. This eliminates the need for component swap in each block. After placing the first block, the program scans the netlist and schematic PDF to identify matches between components and blocks. Since the configuration of the PCB frequently consists of functionally identical parts, Copy Block saves time during PCB design. The program is written in Skill and is based on data deriving from the netlist and schematic PDF files. Data is processed in Excel VBA. Another example of a customized application is BGA Auto Grid, which automatically defines the grid of BGA components based on the pitch between pins. The program enables the accurate and rapid placement of small components like 0402 and 0201 packages, which must be placed at the closest possible distance to a BGA’s legs in order to obtain better filtering, clock resistance, etc. BGA Auto Grid saves substantial time in component placement, as it would no longer be necessary to manually measure the distance between these small components and the vias. Further, it ensures that the components are assembled accurately between the vias. Requirements for these applications come not only from PCB designers, but also from customers and development engineers, who sometimes are required to prepare dedicated MAY 2008 designs. The programs are adapted to the nature of their work and are aimed at making development and design processes effective. For example, a customer’s footprints library may use different symbol components with identical names. This is a result of a non-uniform definition of components in the drawing tools. A request was made to write a program in Skill to compare components with identical names and find the difference between them, in terms of the critical parameters for PCB design, such as height, or the padstacks that were used to prepare them. This is how Compare Two DRAs was born. The program produces a report showing definition of symbols (height, distance between pads, etc.). Another advantage in the use of customized programs is a reduction in malfunctions during the design process. Instead of the designer executing actions manually, they are automated in the service programs, thus minimizing human error. The following are two examples of projects demonstrating the savings obtained using these customized applications. PCB A was manufactured without the use of these auxiliary programs. PCB B, on the other hand, was designed using many of the 22 applications developed. TABLE 1 shows the work hours invested in the design of both cards. In each one of the design phases, the number of invested hours was measured. In two stages of the design process – silk and assembly (SA) and MFG (preparation of the manufacturing file), use of the programs significantly reduced working time. For example, SA activities in PCB A took 32 hours, whereas in PCB B it took only 6.6 hours. For a reliable, accurate measurement, the hours invested in these two phases were normalized for each of the projects. A summary of the results demonstrates that the accumulated savings obtained by the use of these programs reached 290%! In a project with 10,000 pins, timesavings reached 34 hours (more than 3 work days). In a project with 20,000 pads, the savings reach 66 hours (more than a work week). FIGURE 1 graphically depicts the number of hours invested in SA and MFG for a project with 10,000 pads. In summary, time-to-market is crucial to the success of an electronic product. An evaluation of all stages of the lifecycle of a prototype, and locating the areas in which it is possible to save time to make processes more efficient can significantly improve TTM. This article presented a proven method for shortening PCB design time by using dedicated customized software applications implemented in the EDA tool. PCD&F ARBEL NISSAN is COO of CircuTec; ArbelN@nistecgroup.com. PRINTED CIRCUIT DESIGN & FAB 25

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - May 2008

Printed Circuit Design & Fab - May 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC For the Real World PCB East Conference Brochure Positive Plating Don't Let your Signals Stub Their Toes Improve PCB Layout With Skill Utility Programs The Next Generation Design Tool Challenge Thermally Conductive Microwave Materials PCB Dielectric Degradation in Lead-Free Assembly Applications A Tale of Two Trade Shows Eliminating Board Defects Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - May 2008

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