Printed Circuit Design & Fab - May 2008 - (Page 36) LEAD-FREE RELIABILITY of material strength. One of the early descriptors for a PCB was “organic wiring boards,” because the epoxy is an organic based chemistry that can degrade over time, even at ambient temperatures. There is a tendency to think that the increased forces applied to the PCB in lead-free assembly are causing failure. Note that we are not differentiating between normal and shear stress, but rather the combination of all forces. It is more likely that material degradation is working in concert with increased stress, which results in catastrophic failure of the material. Leadfree assembly and rework may initiate material damage, which can develop further over time. In cohesive failures, cracks propagate across the materials and are not limited to a material interface. The crack may change directions producing sharp angles, have an irregular thickness and end in blunt points. The crack may follow glass fibers and then cross into resin rich areas of the dielectric. The crack may be oriented in a horizontal or vertical plane and traverses between B- and C-stage layers. This failure mode maybe accelerated with out-gassing volatiles, but may not be presented as a classic blister or bubble shape. These failures also contain a mechanical component in that a number of specific design attributes (e.g. grid spacing below 0.040 inch, multiple central planes, heavier copper planes, etc.) tend to be more prone to this type of failure. Crazing. This condition may be described as a separation between the epoxy and individual glass fibers. This is a more insidious failure mode, in that there are no obvious visible cracks, but it can be seen as light refraction observed along glass fibers that are parallel with the plane of the microsection, as seen in FIGURE 4. There is a reluctance to label this condition as delamination, but the effects are similar. Capacitance changes are observed if this condition develops or increases in response to thermal excisions associated with assembly, rework or reliability testing. Dark field microscopy may be useful to better visualize the magnitude of glass to resin separation. The light refraction appears to be due to a small separation of the epoxy and the glass fabric. Viewed end on, the glass fibers appear to have black lines around bundles or individual fibers that present as crescent shaped lines. This failure mode can extend CTF in reliability testing, but does not accelerate failures. Crazing is thought to play a role in CAF type failures by providing a path for electro-chemical migration. The size of these cracks promotes capillary action if liquids are present. If crazing occurs before aqueous processes during fabrication, then liquids may penetrate along the glass fibers. This situation is further exacerbated by the presence of an electrical bias, which can cause the migration of ionic contaminants, bridging between adjacent features. This condition is implicated in field failures that are developed over time, particularly when there is high electrical bias in a humid environment accompanied by thermal cycling. Dielectric Decomposition. This failure mode is rarely expressed in reliability testing. Dielectric decomposition presents as a charred material. The boards or coupons may look dark brown to black, and in extreme cases carbonized balls may be present beside the vias as shown in FIGURE 5. In microscopic examination, the material presents as round voids resembling bubbles, and there is extreme deformation of copper traces and pad rotation. Out-gassing is obvious, in that the material looks as if it has boiled. Surprisingly, circuit conductivity may not be 36 degraded by material decomposition if the internal interconnections (barrels and copper posts) are well made. There is a fifth material condition that is not found by capacitance testing but should be noted. The condition has been described as “cratering,” where a surface mount pad develops a crack in the butter coat (resin rich area) on the surface of the material (FIGURE 6). The failure mode is created when the pad and attached material break away from the surface of the board. This failure mode is associated with an interaction between the PCB, components and assembly processes. Another example is the case where the plated through hole has lifted pads (FIGURE 7). The area where the dielectric remains attached to the lifted copper may be related to this failure mode. Material degradation can be created during assembly, during rework, or thermal cycling occurring over time in the end use environment. Some materials that survive lead-free assembly and rework in a product that is less complex, such as lower layer counts and low aspect ratio construction PCBs, may fail in high layer count, high aspect ratio applications. In general, material degradation is more likely to be found in products designed with a thickness greater than 0.075 inch (1.9 mm), with high layer counts (12+), higher densities (less than 0.040 inch or 1 mm grid) and high aspect ratio vias (5 to 1 or greater). There is an increased vulnerability for delamination in PCBs constructed with sequential laminations (two or more lamination cycles). This may be due to internal dielectric layers being exposed to multiple curing cycles. PCBs, fabricated with high speed materials, and in low loss and elevated frequency applications are also more vulnerable to material degradation associated with lead-free assembly. The common industry response to material degradation has been to bake boards before assembly and rework. The baking is done in an effort to remove volatiles, specifically water. Traditional low temperature (105˚C) baking to remove water has demonstrated limited success. Aggressively applied, baking may further degrade the dielectric material. Aggressive baking can also degrade the surface finishes making soldering problematic. Excessive baking by either higher temperature or extended times may be considered another thermal excursion, adding to the degradation of the material prior to assembly and rework. The best approach to meeting the reliability challenges of lead-free assembly and rework is to achieve a balance in the fabrication process, the material used, and the PCB design. Optimizing these three influences may produce synergy for extended reliability in a given application. Each PCB is unique by design, by the fabricators processes and by the materials used. What is reliable in one application may not be reliable in another. Each application requires objective evaluation, based on experience and confirmed by testing, to meet the lead-free reliability challenge. PCD&F ACKNOWLEDGEMENTS Appreciation is extended to Bill Birch, Jason Furlong and the team at PWB Interconnect Solution Inc. Ottawa Ontario Canada. PAUL REID is Program Coordinator at PWB Interconnect Solutions, in Ottawa, Ontario, Canada; Paul.Reid@mail.pwbcorp.com. MAY 2008 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - May 2008 Printed Circuit Design & Fab - May 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC For the Real World PCB East Conference Brochure Positive Plating Don't Let your Signals Stub Their Toes Improve PCB Layout With Skill Utility Programs The Next Generation Design Tool Challenge Thermally Conductive Microwave Materials PCB Dielectric Degradation in Lead-Free Assembly Applications A Tale of Two Trade Shows Eliminating Board Defects Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - May 2008 Printed Circuit Design & Fab - May 2008 - Printed Circuit Design & Fab - May 2008 (Page Cover1) Printed Circuit Design & Fab - May 2008 - Printed Circuit Design & Fab - May 2008 (Page Cover2) Printed Circuit Design & Fab - May 2008 - Printed Circuit Design & Fab - May 2008 (Page 1) Printed Circuit Design & Fab - May 2008 - Contents (Page 2) Printed Circuit Design & Fab - May 2008 - Contents (Page 3) Printed Circuit Design & Fab - May 2008 - Our Line (Page 4) Printed Circuit Design & Fab - May 2008 - Our Line (Page 5) Printed Circuit Design & Fab - May 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - May 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - May 2008 - Around the World (Page 8) Printed Circuit Design & Fab - May 2008 - Around the World (Page 9) Printed Circuit Design & Fab - May 2008 - Around the World (Page 10) Printed Circuit Design & Fab - May 2008 - Around the World (Page 11) Printed Circuit Design & Fab - May 2008 - Happenings (Page 12) Printed Circuit Design & Fab - May 2008 - Happenings (Page 13) Printed Circuit Design & Fab - May 2008 - ROI (Page 14) Printed Circuit Design & Fab - May 2008 - ROI (Page 15) Printed Circuit Design & Fab - May 2008 - EMC For the Real World (Page 16) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-1) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-2) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-3) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-4) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-5) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-6) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-7) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-8) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-9) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-10) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-11) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-12) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-13) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-14) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-15) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page PCB-16) Printed Circuit Design & Fab - May 2008 - PCB East Conference Brochure (Page 17) Printed Circuit Design & Fab - May 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - May 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 20) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 21) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 22) Printed Circuit Design & Fab - May 2008 - Don't Let your Signals Stub Their Toes (Page 23) Printed Circuit Design & Fab - May 2008 - Improve PCB Layout With Skill Utility Programs (Page 24) Printed Circuit Design & Fab - May 2008 - Improve PCB Layout With Skill Utility Programs (Page 25) Printed Circuit Design & Fab - May 2008 - The Next Generation Design Tool Challenge (Page 26) Printed Circuit Design & Fab - May 2008 - The Next Generation Design Tool Challenge (Page 27) Printed Circuit Design & Fab - May 2008 - The Next Generation Design Tool Challenge (Page 28) Printed Circuit Design & Fab - May 2008 - Thermally Conductive Microwave Materials (Page 29) Printed Circuit Design & Fab - May 2008 - Thermally Conductive Microwave Materials (Page 30) Printed Circuit Design & Fab - May 2008 - Thermally Conductive Microwave Materials (Page 31) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 32) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 33) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 34) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 35) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 36) Printed Circuit Design & Fab - May 2008 - PCB Dielectric Degradation in Lead-Free Assembly Applications (Page 37) Printed Circuit Design & Fab - May 2008 - A Tale of Two Trade Shows (Page 38) Printed Circuit Design & Fab - May 2008 - A Tale of Two Trade Shows (Page 39) Printed Circuit Design & Fab - May 2008 - Eliminating Board Defects (Page 40) Printed Circuit Design & Fab - May 2008 - Eliminating Board Defects (Page 41) Printed Circuit Design & Fab - May 2008 - Eliminating Board Defects (Page 42) Printed Circuit Design & Fab - May 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - May 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - May 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - May 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - May 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - May 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - May 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - May 2008 - BGA Bulletin (Page Cover4)
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