Antenna Systems & Technology - Winter 2015 - (Page 8)

FEATURE ARTICLE A New Leap Towards True Software-Defined Radio By Tommy Neu, Systems Engineer | Texas Instruments Recent industry advances in RF sampling analog-to-digital converters (ADCs) add further support to the system designers envisioning a true software-defined radio (SDR) where a receiver consists only of a low-noise amplifier (LNA), a filter and the ADC. In cellular infrastructure, for example, where the RF bands span from 700 MHz to 3.8 GHz, this vision will soon become a reality as demands for smaller form factors, lower system power consumption and much higher density will be met as more capable devices become available. Modern high-performance receivers primarily use a heterodyne architecture, where the input signal resides at an RF range from 700 MHz to many Gigahertz, and gets down-converted to a low IF between DC-500 MHz. In some applications like military radars, the 1 to 3 GHz range (S-band, L-band) is used as a secondary IF when down-converting from a much higher, primary RF band in the 10 GHz (Xband) or 25 to 40 GHz (Kaband), for example. Figure 1. Traditional heterodyne architecture versus using RF sampling ADCs. The RF sampling ADC directly samples the RF input and thus replaces one entire down conversion stage as shown in Figure 1. This saves PCB area as the RF local oscillator (LO), mixer and additional gain and filtering stages are removed, enabling much more compact system designs. The Gigahertz sampling clock of the ADC effectively acts like the LO, down converting the sampled RF energy to a lower digital intermediate frequency, if the input is in the 2nd Nyquist zone or higher). Like the mixer LO in a heterodyne architecture, the ADC clock requires very good phase noise to prevent energy from large signals mixing to the same frequency as small signals, reducing receiver sensitivity. Traditional RF sampling ADCs require a very wide digital interface to output the data. Since low-voltage differential signaling (LVDS) is typically used only up to ~1 Gbps, a 12-bit, 4 Gsps ADC, for example, would require about 49 differential pairs (48 for data, one for clock). This demands a big package and a large routing area on the PCB. The ADC12J4000, for example, uses a 10 Gbps JESD204b interface, which transmits the same amount of data over just eight differential pairs - a reduction of 83 percent (Figure 2). For narrowband applications, on-chip digital decimation filter (DDC) allows for on-chip filter- Figure 2. Digital interface of RF ing to further reduce the data traffic and number of lanes needed. A with LVDS or JESD204B interface. signal of 100 MHz bandwidth, for instance, can be transmitted with 250 Msps (decimation by 32 with IQ output) using just a single lane at 5 Gbps. 8 Antenna Systems & Technology Winter 2015 ADC www.AntennasOnline.com http://www.AntennasOnline.com

Table of Contents for the Digital Edition of Antenna Systems & Technology - Winter 2015

Table of Contents
Editor’s Choice
A New Leap Towards True Software-Defined Radio
SON: The Future of LTE Network Deployments and Operations
Manufacturing of Zero-Centered Antennas for High Precision Positioning with Global Navigation Satellite Systems
Mission-Critical Flight Line Testing
Antennas
Components/Subsystems
Test & Measurement
Industry News
Marketplace
Tighter PIM Requirements for Multiband DAS

Antenna Systems & Technology - Winter 2015