Electronics Protection - Fall 2014 - (Page 6)
Build Reliable Circuits Faster by Discovering the
"Dirty Little Secrets" of ESD Protection Device Specifications
Chad Marak, Director of Technical Marketing and TVS Diode
Array Product Line, Littelfuse, Inc.
Without sufficient protection, electronic devices have always
been susceptible to damage from electrostatic discharge (ESD)
or other overvoltage events. Today, unfortunately, these products
have even less tolerance for DC voltages higher than 3.3 V, so an
ESD pulse can prove catastrophic. A variety of factors contribute
to this reduced voltage tolerance, including the smaller manufacturing geometries of today's most advanced ICs. The level of
on-chip protection has also declined. However, perhaps the most
significant factor is the enormous popularity of mobile devices like
ultrabooks, tablets, smartphones, mp3 players, digital cameras, etc.
Their mobile nature means they are used "on the go" in uncontrolled and potentially static-filled environments, with only the
on-board circuit protection to safeguard them from an unexpected zap. Ensuring the longevity of these devices demands careful
location and selection of appropriate ESD protection devices on
the printed circuit board (PCB).
An ESD protection device's main purpose is to provide the lowest resistance shunt path to ground during an overvoltage event
or transient. Proper PCB layout/trace routing is critical to using
ESD protection devices effectively. Even the most ideal protection
solution can be rendered useless if the proper layout techniques
aren't used. Perhaps the most common type of location error
among new circuit designers is placing the ESD protection device
"wherever it fits" on the board on the bus or data line to be protected, rather than taking the time to reorganize the board layout
to allow placement of the device right at the port that's subject
to ESD or electrical overstress condition. The selected device
should be placed as close to the connector or button/switch being
protected as is practicable. This will ensure that the ESD transient
is clamped as soon as it enters the circuit. Also, the device should
be installed as close as possible to the data/signal line as possible,
avoiding stub traces if feasible. This will eliminate the potential
for an inductive overshoot that would result in a voltage spike
that could damage the circuitry.1 Obviously, however, choosing the
right device is just as important as creating the optimum layout.
Even though the specifications for the several of the same type
of ESD device from different manufacturers may seem to indicate
that they offer equivalent performance, it's not always safe to
assume that they all provide the same degree of protection. Take
the extra time necessary to review all specifications thoroughly,
including all the associated footnotes, before deciding that a
device is appropriate for a specific ESD protection application.
That includes both the lists of electrical parameters and the plots
outlining device performance. For example, in some vendors' data
sheets, the plots illustrating a device's "clamping voltage" that
show an ESD waveform often don't provide information that's particularly relevant to the concerns of circuit or hardware designers.
In some cases, the clamping voltage of these devices is specified
using ESD pulse levels far lower than the industry standard of 8
kV (such as 2 kV, 4 kV or 6 kV). Although the resulting waveform
plot, or clamping voltage, may leave the reader with a positive
impression of the device, a closer reading of the footnotes may
reveal that the plot is irrelevant to a real-world application of a
consumer using an electronic product.
Here's one telltale sign of a spec that's just too good to be true.
Check for specifications based non-relevant pulse waveforms, such
Fall 2014 * www.ElectronicsProtectionMagazine.com
as the pulse waveform specified by the Human-Body Model [HBM]
standard, which was originally developed as part of a MIL-STD-883,
Method 3015.8, Electrostatic Discharge Sensitivity Classification.
This standard is relevant only to the manufacturing environment
with ESD grounding/wrist straps, etc., such as an IC on an assembly line. However, less scrupulous vendors may choose to use this
HBM pulse during testing because it puts less energy (i.e., less current) through the protection device under test, which makes the
resulting clamping voltage specification look much better.
The relevant pulse waveform and standard for designing everyday ESD protection into electronic products comes from the
International Electrotechnical Commission's IEC61000-4-2 standard. This standard is a system-level test that replicates a charged
person discharging to electronic equipment in the end-user environment. The purpose of the system-level test is to ensure that
finished products can survive normal operation. It assumes that
the product's user won't take any precautions to lower ESD stress.
When evaluating the clamping voltage of a device claimed to
be measured under an IEC61000-4-2 waveform, be aware that
less-scrupulous vendors might provide a plot indicating a low
clamping voltage but won't note the size of the external attenuator they used between the DUT and the oscilloscope to obtain the
plot. Without this attenuator information, there's no way to interpret the numbers associated with the waveform plot accurately.
Look for notes like "A 10x attenuator was used" so you'll know
what to multiply the numbers in the plot by to assess the device's
actual response to an ESD pulse unless noted that the attenuation
correction has already been done.
Be on the lookout for disconnects between the information in
the plots and the electrical characteristics. Usually, any "fudging"
goes on in the plots. Figure 1 is an example of one vendor's "overshoot and clamping plot," which purports to show the result of an
ESD test pulse of 25 kV with a 1/30 nanosecond waveshape. The
waveshape does not directly relate to any standard ESD pulse from
either the IEC or HBM standard. It could be used to approximate
either standard, but the reader would have to know which one
because the amount of energy is so different between the two.
Figure 1. A misleading overshoot and clamping plot.
The 30 nanosecond point (the 50 percent point of the fall time)
is also atypical. This is typically how a lightning pulse is stated and,
therefore, the test pulse being used may not have as much energy
as a standard IEC pulse and is not directly comparable on a one-
Table of Contents for the Digital Edition of Electronics Protection - Fall 2014
Turn up the Heat and Chill Out: How IT Executives Can Reduce Data Center Cooling Costs
Build Reliable Circuits Faster by Discovering the "Dirty Little Secrets" of ESD Protection Device Specifications
About MicroTCA 4.0: A High-Performance Architecture with I/O and Signal Conditioning Provisions
LED Thermal Management: Passive Solutions for High Heat Plux Applications
Minimizing CPU Overheating with Liquid Cooling
Calendar of Events
Electronics Protection - Fall 2014