Xcell China 26

技術專欄 IDDR 的作用是將來自 ADC 的快速輸入數字信號去復用 (de-multiplex) 為兩個單倍數據速率數據流，每一個單倍數據速率數據流占一半的 ADC 採樣率。對於一個 2 倍多相抽取濾波器來說，這無疑是個理想的格式。使用 Virtex-5 DSP48E，每個子濾波器可維持 550 MSPS，實現最大為 1.1 GSPS 的 ADC 採樣率。同樣， Spartan-3A DSP 可維持 500 MSPS 的 ADC 採樣率。伴隨更快的 ADC 採樣率而來的，是提供能將數據鎖存到 FPGA 中的更小的數據有效窗口這一難題。而且，ADC 數據字精度越寬，佈局任務就越艱巨，在數據總線上各個信號發生歪斜的可能性就越高，從而導致數據損壞。Virtex-5 FPGA 提供稱為“IODELAY”的一種可靠解決方案，這是包含在每一個 I/O 模塊中的可編程延遲單元。IODELAY 可以逐個對數據總線中的信號進行時移，以將數據有效窗口準確定位到半速率數據就緒信號 (DRY) 的最佳轉換點。圖 1 說明 Virtex-5 器件中用於實現高性能 ADC 接口的獨特功能。為將採樣抖動降至最低，ADC 將源同步數據就緒信號與數據一起發出，與此同時，干凈的低抖動採樣時鐘不經 FPGA 而直接布線到 ADC。高性能 DAC (數模轉換器) 接口在數據字精度相等的情況下，數模轉換器 (DAC) 的採樣率通常要比 ADC 的採樣率高，這就造成在信號鏈的 DAC 極限下出現巨大的設計難題。Virtex-5 架構的幾個功能有助於克服這一難題。連接到 Texas Instruments (TI) DAC5682Z（16 位雙 DAC，採樣率為 1 GSPS，LVDS 信號輸入）的 Virtex-5 接口不失為一個很好的例子。在實際系統中，只需將 1 GSPS 的採樣率部署到 DAC 的最後輸出階段，而 FPGA 信號處理鏈的中間階段以與信號帶寬成比例的較低的採樣率工作。這使我們在中間處理階段擁有較慢的系統時鐘，其好處是簡化時序收斂、降低功耗。跟 ADC 的情況一樣，多相濾波器是在信號鏈的 DAC 端實現採樣率改變的高效 DSP 結構。為達到 TI DAC5682Z 1 GSPS 的輸出採樣率，一個 2 倍多相插補濾波器使用兩個子濾波器，每個具有 500 MSPS 的吞吐量。這些採樣率是在 Virtex-5 DSP48E slice 的性能規格範圍內。需要使用一個多路復用器將子濾波器的輸出結合在一起，以從多相插補濾波器獲得快速輸出率。對於 1 GSPS 的輸出採樣率，建議將多相插補多路復用器放置到離驅動 DAC5682Z 的 LVDS 輸出緩衝盡可能近的位置。Virtex-5 FPGA 在 I/O 模塊中提供了一個專用資源，能完美地實現上述目標：ODDR（輸出雙倍數據速率）寄存器。此 ODDR 直接布線到快速 LVDS 差分輸出緩衝，可維持 1 GSPS（和更高）的輸出採樣率，同時又維持了 PCB 上的信號完整性。圖 2 – DAC：多相插補 + ODDR + LVDS Sub-Phase 1 I/O Block DATA 2X Polyphase Decimator Sub-Phase 0 XtremeDSP XtremeDSP IDDR ADC DRY Low-Jitter Sampling Clock IODELAY Sub-Phase 1 圖 1 – 高性能 ADC 接口 2X Polyphase Interpolator Sub-Phase 0 I/O Block ODDR XtremeDSP XtremeDSP IODELAY DAC Virtex-5 FPGA Low-Jitter Sampling Clock 結論在本文中，我們展示了使用 Xilinx Virtex-5 FPGA 的混合信號系統專用 DSP 和接口技術。您可以使用 Virtex-5 器件的關鍵功能來維持現代高性能數據轉換器的優異 SNR 規格，優化系統的性能。本文中所描述的技術將在 2007 Speedway 大會的 DSP 專題研討會上亮相，該研討會由 Avnet 數據轉換器主要提供商 Texas Instruments、Analog Devices、National Semiconductor 協辦。欲瞭解詳情，請訪問。 11 賽靈思中國通訊 26期 http://em.avnet.com/xilinxspeedway http://em.avnet.com/xilinxspeedway

Table of Contents Feed for the Digital Edition of Xcell China 26

Xcell China 26 Avnet Selecting the Right Inteconnect Scaling Chip-to-Chip Interconnect Made Simple PCI Express and FPGAs Virtex-5 FPGA Techniques for High-Performance Data Converters Automated MGT Serial Link Tuning Ensures Design Margins Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape Reducing CPU Load for Ethernet Applications A High-Speed Serial Connectivity Solution with Aurora IP Serial RapidIO Connectivity Enhances DSP Co-Processing The NXP/PLDA Programmable PCI Express Solutions Create Memory Inteface Designs Faster with Xilinx Solutions Driving Home Multimedia Making the Most of MOST Control Messaging Leveraging HyperTransport on Xilinx FPGAs FPGA-Based Simulation for Rapid Prototyping Xilinx Spartan-3 DDR-400 Xilinx training courses Oct-Dec Excelpoint Xilinx

Xcell China 26 - Xcell China 26 (Page 1) Xcell China 26 - Avnet (Page 2) Xcell China 26 - Avnet (Page 3) Xcell China 26 - Selecting the Right Inteconnect (Page 4) Xcell China 26 - Scaling Chip-to-Chip Interconnect Made Simple (Page 5) Xcell China 26 - Scaling Chip-to-Chip Interconnect Made Simple (Page 6) Xcell China 26 - PCI Express and FPGAs (Page 7) Xcell China 26 - PCI Express and FPGAs (Page 8) Xcell China 26 - PCI Express and FPGAs (Page 9) Xcell China 26 - Virtex-5 FPGA Techniques for High-Performance Data Converters (Page 10) Xcell China 26 - Virtex-5 FPGA Techniques for High-Performance Data Converters (Page 11) Xcell China 26 - Automated MGT Serial Link Tuning Ensures Design Margins (Page 12) Xcell China 26 - Automated MGT Serial Link Tuning Ensures Design Margins (Page 13) Xcell China 26 - Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape (Page 14) Xcell China 26 - Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape (Page 15) Xcell China 26 - Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape (Page 16) Xcell China 26 - Reducing CPU Load for Ethernet Applications (Page 17) Xcell China 26 - Reducing CPU Load for Ethernet Applications (Page 18) Xcell China 26 - Reducing CPU Load for Ethernet Applications (Page 19) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 20) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 21) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 22) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 23) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 24) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 25) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 26) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 27) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 28) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 29) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 30) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 31) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 32) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 33) Xcell China 26 - Create Memory Inteface Designs Faster with Xilinx Solutions (Page 34) Xcell China 26 - Create Memory Inteface Designs Faster with Xilinx Solutions (Page 35) Xcell China 26 - Create Memory Inteface Designs Faster with Xilinx Solutions (Page 36) Xcell China 26 - Driving Home Multimedia (Page 37) Xcell China 26 - Driving Home Multimedia (Page 38) Xcell China 26 - Driving Home Multimedia (Page 39) Xcell China 26 - Making the Most of MOST Control Messaging (Page 40) Xcell China 26 - Making the Most of MOST Control Messaging (Page 41) Xcell China 26 - Making the Most of MOST Control Messaging (Page 42) Xcell China 26 - Leveraging HyperTransport on Xilinx FPGAs (Page 43) Xcell China 26 - Leveraging HyperTransport on Xilinx FPGAs (Page 44) Xcell China 26 - Leveraging HyperTransport on Xilinx FPGAs (Page 45) Xcell China 26 - FPGA-Based Simulation for Rapid Prototyping (Page 46) Xcell China 26 - FPGA-Based Simulation for Rapid Prototyping (Page 47) Xcell China 26 - Xilinx training courses Oct-Dec (Page 48) Xcell China 26 - Excelpoint (Page 49) Xcell China 26 - Xilinx (Page 50) http://www.nxtbookMEDIA.com

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