Xcell China 26 - (Page 7) 技 術 專 欄 PCI Express 與 FPGA FPGA 為何是構建 PCI Express 端點器件的最佳平台 作者：Alex Goldhammer Xilinx 公司 平台解決方案部門技術營銷經理 alex.goldhammer@xilinx.com PCI Express 是一種使用時鐘數據恢復 (CDR) 技術的高速串行 I/O 互連機制。PCI Express Gen1 規範規定的線速率為每通道 2.5 Gbps，可以讓您建立具備單通道 (x1) 鏈路 2 Gbps（經 8B/10B 編碼）直至 32 通 道 64 Gbps 吞吐量的應用。這樣，就能在 保持或改進吞吐量的同時，顯著減少引腳 數量。另外，還可以減小 PCB 的尺寸、降 低跡線和層的數量並簡化佈局和設計。引 腳數量減少，也就意味 噪聲和電磁干擾 (EMI) 降低。CDR 消除了寬並行總線中普遍 存在的時鐘-數據歪斜問題，簡化了互連 實現。 PCI Express 互連架構主要針對基於 PC （台式/膝上）的系統。但就像 PCI 一 樣，PCI Express 也很快轉移到其他系統類 型，如嵌入式系統。它規定了三種類型 器件：根聯合體 (root complex)、交換器件 和端點（圖 1）。根聯合體大致等同於 PCI 主機，CPU、系統存儲器和圖形控制 器與之相連接。由於 PCI Express 的點對點 特性，必須使用交換器件來增加系統功 能的數量。PCI Express 交換器件將上游端 的根聯合體器件連接到下游端的端點。 端點功能類似於 PCI/PCI-X 器件。最常 用的端點器件有以太網控制器或存儲 HBA （主機總線適配器）。FPGA 最常用於數 據處理和橋接功能，所以其最大目標功能 就是端點。FPGA 實現非常適合於視頻、 醫療影像、工業、測試和測量、數據採集 和存儲應用。 PCI-SIG（PCI 特別興趣小組）採用的 PCI Express 規範規定每個 PCI Express 器件使 用三個不同的協議層：物理層、數據鏈路 層和事務層。您可以使用單芯片或雙芯片 解決方案來構建 PCI Express 端點。例如， 使用 Xilinx® SpartanTM-3 器件之類的低成本 FPGA，您可以用商用離散 PCI Express PHY （圖 2）來構建數據鏈路和事務層。此選 項最適合於 x1 通道應用，如：總線控制 器、數據採集卡和提高性能的 PCI 32/33 器件。或者，您可以使用類似 Virtex TM -5 LXT 或 SXT FPGA 的單芯片解決方案，它們 具備集成的 PCI Express PHY。此選項最適 合於通訊或高清晰度音頻/視頻端點器件 （圖 3），它們對性能的要求更高：x4（8 Gbps 吞吐量）鏈路或 x8（16 Gbps 吞吐 量）鏈路。 7 賽靈思中國通訊 26期 ©2007 Xilinx Inc. 版權所有。XILINX、Xilinx 標誌以及本文件中包括的其他品牌名稱，是 Xilinx, Inc. 的商標。所有其他商標都是其各自所有者的財產。
Table of Contents Feed for the Digital Edition of Xcell China 26 Xcell China 26 Avnet Selecting the Right Inteconnect Scaling Chip-to-Chip Interconnect Made Simple PCI Express and FPGAs Virtex-5 FPGA Techniques for High-Performance Data Converters Automated MGT Serial Link Tuning Ensures Design Margins Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape Reducing CPU Load for Ethernet Applications A High-Speed Serial Connectivity Solution with Aurora IP Serial RapidIO Connectivity Enhances DSP Co-Processing The NXP/PLDA Programmable PCI Express Solutions Create Memory Inteface Designs Faster with Xilinx Solutions Driving Home Multimedia Making the Most of MOST Control Messaging Leveraging HyperTransport on Xilinx FPGAs FPGA-Based Simulation for Rapid Prototyping Xilinx Spartan-3 DDR-400 Xilinx training courses Oct-Dec Excelpoint Xilinx Xcell China 26 Xcell China 26 - Xcell China 26 (Page 1) Xcell China 26 - Avnet (Page 2) Xcell China 26 - Avnet (Page 3) Xcell China 26 - Selecting the Right Inteconnect (Page 4) Xcell China 26 - Scaling Chip-to-Chip Interconnect Made Simple (Page 5) Xcell China 26 - Scaling Chip-to-Chip Interconnect Made Simple (Page 6) Xcell China 26 - PCI Express and FPGAs (Page 7) Xcell China 26 - PCI Express and FPGAs (Page 8) Xcell China 26 - PCI Express and FPGAs (Page 9) Xcell China 26 - Virtex-5 FPGA Techniques for High-Performance Data Converters (Page 10) Xcell China 26 - Virtex-5 FPGA Techniques for High-Performance Data Converters (Page 11) Xcell China 26 - Automated MGT Serial Link Tuning Ensures Design Margins (Page 12) Xcell China 26 - Automated MGT Serial Link Tuning Ensures Design Margins (Page 13) Xcell China 26 - Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape (Page 14) Xcell China 26 - Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape (Page 15) Xcell China 26 - Xilinx FPGAs Adapt to Ever-Changing Broadcast Video Landscape (Page 16) Xcell China 26 - Reducing CPU Load for Ethernet Applications (Page 17) Xcell China 26 - Reducing CPU Load for Ethernet Applications (Page 18) Xcell China 26 - Reducing CPU Load for Ethernet Applications (Page 19) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 20) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 21) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 22) Xcell China 26 - A High-Speed Serial Connectivity Solution with Aurora IP (Page 23) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 24) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 25) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 26) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 27) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 28) Xcell China 26 - Serial RapidIO Connectivity Enhances DSP Co-Processing (Page 29) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 30) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 31) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 32) Xcell China 26 - The NXP/PLDA Programmable PCI Express Solutions (Page 33) Xcell China 26 - Create Memory Inteface Designs Faster with Xilinx Solutions (Page 34) Xcell China 26 - Create Memory Inteface Designs Faster with Xilinx Solutions (Page 35) Xcell China 26 - Create Memory Inteface Designs Faster with Xilinx Solutions (Page 36) Xcell China 26 - Driving Home Multimedia (Page 37) Xcell China 26 - Driving Home Multimedia (Page 38) Xcell China 26 - Driving Home Multimedia (Page 39) Xcell China 26 - Making the Most of MOST Control Messaging (Page 40) Xcell China 26 - Making the Most of MOST Control Messaging (Page 41) Xcell China 26 - Making the Most of MOST Control Messaging (Page 42) Xcell China 26 - Leveraging HyperTransport on Xilinx FPGAs (Page 43) Xcell China 26 - Leveraging HyperTransport on Xilinx FPGAs (Page 44) Xcell China 26 - Leveraging HyperTransport on Xilinx FPGAs (Page 45) Xcell China 26 - FPGA-Based Simulation for Rapid Prototyping (Page 46) Xcell China 26 - FPGA-Based Simulation for Rapid Prototyping (Page 47) Xcell China 26 - Xilinx training courses Oct-Dec (Page 48) Xcell China 26 - Excelpoint (Page 49) Xcell China 26 - Xilinx (Page 50)
For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.