Xcell China 27 - (Page 19) 技 術 專 欄 在較高層進行設計 IP-Explorer 顯著提高了 DSP 硬件設計的抽象層，使其 更接近 DSP 算法開發的抽象層。基本 MATLAB 語言基元 提供了在低層建立任意函數或算法模型的能力，從而形 成了這種抽象層金字塔（圖 3）的基礎。IP-Explorer 將 MATLAB 的標準預配置 DSP 構建模塊和函數庫直接指向硬 件內部，因此顯著提高了這一抽象層。 正弦/余弦架構 六個 CORDIC 架構 由 IP-Explorer 選擇 面積（LUT 數） 2,670 1,287 性能 8.4MSPS 100MSPS 錶 1 – CORDIC 方法和 IP-Explorer 選擇方法的面積和性能結果 Dynamic Range Requirements Library of Hardware Architectures Bipartite Tables Linearly Interpolated LUT Resource Shared – Non-Pipelined CORDIC Resource Shared – Pipelined CORDIC Non-Resource – Non-Pipelined CORDIC 設計示例 為了說明 IP-Explorer 對設計的作用， 請思考圖 4 所示示例：這是一種歐拉角 對四元數的角轉換算法，對三個輸入角 進行正弦和余弦運算。在此示例中，各 輸入的字長為 12 位。 我們對照 IP-Explorer 比較一種典型方 sphi = sin(0.5*phi); Dynamic Constraints 圖 2 – 根據設計的具體情況自動插入 IP 法，即：根據 CORDIC 方法設計三角函數 的一個實現，其後對其進行多次例化。 錶 1 所示為兩種方法的面積和性能結 果。 USM, GPS IP-Explorer 選擇二部錶方法，因為輸 Algorithms 入位寬相當小。第二點好處是這種方法 利用了FPGA 器件的內置 DSP 模塊。否 則，這種方法不會成為 ASIC 的最佳選 擇。這種方法不僅免除了為正弦和余弦 函數設計硬件的任務，而且還可節省面 積 33% 和提高性能 12 倍。 OFDM, 802.XX, Kalmann Reference Designs FFT, Filter, SVD, QRD Functions AccelDSP IP-Explorer Sin, Cos, Sqrt, Div Basic Building Blocks 結論 If, For, While Language Primitives IP-Explorer 代錶 DSP 硬件開發領域 的真正獨一無二的進步。它為關鍵 DSP 圖 3 – DSP 設計的抽象層金字塔 構建模塊提供了一條通向硬件的暢通之 路，從而將硬件設計顯著提高到更接近 使用 MATLAB 的算法開發人員喜聞樂見 的抽象層。 function [q] = euler2quat(phi,theta,psi) 12 bits Sin sphi = sin(0.5*phi); cphi = cos(0.5*phi); stheta = sin(0.5*theta); chteta = cos(0.5*theta); spsi = sin(0.5*psi); cpsi = cos(0.5*psi); q(1) = sphi*stheta*spsi+cphi+ctheta+cpsi; q(2) = sphi*ctheta*cpsi-cphi*stheta*spsi; q(3) = cphi*stheta*cpsi+sphi*ctheta*spsi; q(4) = cphi*ctheta*spsi-sphi*stheta*cpsi; Phi Cos Sin Theta Cos Multiply – Add Tree q 下一步（請點擊下列資料了解詳細內容:） 12 bits Psi Sin • 進一步瞭解 AccelDSP 綜合工具 • 免費收聽錄制講座“AccelDSP 起步 教程” Cos 圖 4 – 歐拉角對四元數角轉換器框圖 2007年冬季刊 19 http://china.xilinx.com/ise/dsp_design_prod/acceldsp/index.htm http://china.xilinx.com/support/training/rel/acceldsp.htm
Table of Contents Feed for the Digital Edition of Xcell China 27 Xcell China 27 Avnet Ad Excelpoint Ad Xilinx Ad Table of Contents Virtual Worlds Prototyping Applications with the Spartan-3A DSP Starter Platform The Virtex-5 SXT Option for High-Performance Digital Signal Processing Prototyping Image Processing Applications Integrating HDL Design and Verification with System Generator Automatic IP Block Selection with IP-Explorer Technology Boosting Wireless Subsystem Performance with FPGA Co-Processing Audio Sample Rate Conversion in FPGAs Accelerating System Development Cycles with the Radar Blockset Library Selecting the Right Memory Controller for Real-Time Applications Future-Proofing Military Applications Using FPGAs Processing Signals from Outer Space with BEE2 Programmable Solutions China Xilinx Training Courses Jan - Mar Nu Horizons Ad Xilinx Ad Xcell China 27 Xcell China 27 - Xcell China 27 (Page 1) Xcell China 27 - Avnet Ad (Page 2) Xcell China 27 - Excelpoint Ad (Page 3) Xcell China 27 - Xilinx Ad (Page 4) Xcell China 27 - Table of Contents (Page 5) Xcell China 27 - Virtual Worlds (Page 6) Xcell China 27 - Prototyping Applications with the Spartan-3A DSP Starter Platform (Page 7) Xcell China 27 - Prototyping Applications with the Spartan-3A DSP Starter Platform (Page 8) Xcell China 27 - The Virtex-5 SXT Option for High-Performance Digital Signal Processing (Page 9) Xcell China 27 - The Virtex-5 SXT Option for High-Performance Digital Signal Processing (Page 10) Xcell China 27 - Prototyping Image Processing Applications (Page 11) Xcell China 27 - Prototyping Image Processing Applications (Page 12) Xcell China 27 - Integrating HDL Design and Verification with System Generator (Page 13) Xcell China 27 - Integrating HDL Design and Verification with System Generator (Page 14) Xcell China 27 - Integrating HDL Design and Verification with System Generator (Page 15) Xcell China 27 - Integrating HDL Design and Verification with System Generator (Page 16) Xcell China 27 - Integrating HDL Design and Verification with System Generator (Page 17) Xcell China 27 - Automatic IP Block Selection with IP-Explorer Technology (Page 18) Xcell China 27 - Automatic IP Block Selection with IP-Explorer Technology (Page 19) Xcell China 27 - Boosting Wireless Subsystem Performance with FPGA Co-Processing (Page 20) Xcell China 27 - Boosting Wireless Subsystem Performance with FPGA Co-Processing (Page 21) Xcell China 27 - Audio Sample Rate Conversion in FPGAs (Page 22) Xcell China 27 - Audio Sample Rate Conversion in FPGAs (Page 23) Xcell China 27 - Audio Sample Rate Conversion in FPGAs (Page 24) Xcell China 27 - Audio Sample Rate Conversion in FPGAs (Page 25) Xcell China 27 - Audio Sample Rate Conversion in FPGAs (Page 26) Xcell China 27 - Accelerating System Development Cycles with the Radar Blockset Library (Page 27) Xcell China 27 - Accelerating System Development Cycles with the Radar Blockset Library (Page 28) Xcell China 27 - Accelerating System Development Cycles with the Radar Blockset Library (Page 29) Xcell China 27 - Selecting the Right Memory Controller for Real-Time Applications (Page 30) Xcell China 27 - Selecting the Right Memory Controller for Real-Time Applications (Page 31) Xcell China 27 - Selecting the Right Memory Controller for Real-Time Applications (Page 32) Xcell China 27 - Future-Proofing Military Applications Using FPGAs (Page 33) Xcell China 27 - Future-Proofing Military Applications Using FPGAs (Page 34) Xcell China 27 - Future-Proofing Military Applications Using FPGAs (Page 35) Xcell China 27 - Processing Signals from Outer Space with BEE2 (Page 36) Xcell China 27 - Processing Signals from Outer Space with BEE2 (Page 37) Xcell China 27 - Processing Signals from Outer Space with BEE2 (Page 38) Xcell China 27 - Processing Signals from Outer Space with BEE2 (Page 39) Xcell China 27 - Xilinx Training Courses Jan - Mar (Page 40) Xcell China 27 - Nu Horizons Ad (Page 41) Xcell China 27 - Xilinx Ad (Page 42)
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