EDNE December 2012 - (Page 16)

A mo insight intonthly T&M techn the latest o the pages logy from Measurem of Test & (www.tmw ent World orld.com ) ® Test & Measurement World is the leading monthly magazine for engineers and managers in the electronics testing industry. Test high-speed memory with non-intrusive embedded instruments, Part 3 ® Th e f ir sT a r Ti c l e i n T hi s s e r i e s ( www.edn-europe.com/article.asp?articleid=5787) explained Th e n aTu r e o f T he m e m o ry T e s T c ha lleng e i n Th e i ndusTry To day. Th e sec o nd a r Ticl e ( www.edn-europe.com/article.asp?articleid=5838) i n Th i s Th ree-pa rT seri es o n memo ry TesT de scr ibe d sev e r a l n o n - i n T r u s i v e d ebug a nd TesT Tec h no lo g i es, i nc ludi ng funcTio n a l Te sT, pr o c e s s o r - c o n T r o l l e d TesT, bo unda ry-sca n TesT, fp ga -c o nTro lled TesT a n d oTh e r s. b e g i n n i n g w i T h fu n c T i o na l TesT, Th i s, Th e fi na l a rTi c le i n Th e seri es, Ta k e s a c lo s e r lo o k aT T h e T r a d e o ffs among T he non-in Trusive me Thods and discu sse s h ow T he y hav e b e e n i m p lemenTed i n Th e i ndusTry. Alfred Crouch, ASSET InterTech F unctional test has also been applied to memories for many years, but it can only be brought to bear late in the development cycle when the board is fully functional or close to fully functional. As a result, functional tests are very difficult to apply to boards that have a problem, bug, defect or error. Functional tests typically are applied with the board in a test jig or when the board is in a fully configured system. In addition, their diagnostic granularity may be very limited. PSEUDO-FUNCTIONAL TEST TOOLS (IEEE 1149.1/ JTAG) testers for more than a decade. Currently though, certain new memories may be outpacing the ability of board-level boundary scan since the minimum clock and data rates of the memory devices may exceed the maximum board test clock frequency (TCK) of boundary scan. So, for modern high-speed designs, the application of boundary-scan test (BST) as a tool for memory test may be limited, but only time will tell. FPGA-CONTROLLED TEST TOOLS More recently, third-party pseudo-functional test tools have been able to overcome many of the difficulties of classic functional test and reduce the risks that a test development process late in the design cycle typically poses. For example, processorcontrolled test (PCT) tools for embedded instruments apply pseudo-functional test routines independently of the board’s functional firmware or operating software. PCT test routines can be applied by a processor without requiring a functional firmware environment. PCT tools appropriate the processor’s capabilities by way of its debug port. If the processor is connected directly to on-board memory, a PCT tool can apply its pseudo-functional test routines originating from the processor to test memory. As a result, test teams can apply pseudo-functional memory tests during the early stages of board bring-up without having to wait for the design’s operating firmware. In addition, the validity and comprehensive nature of PCT’s test routines have been verified over many different designs from many board manufacturers. The comprehensiveness of PCT’s memory test routines have themselves been fully field tested. Memory has been tested with standalone boundary-scan FPGA-controlled test (FCT) tools are emerging as an attractive alternative for debugging and testing memory. Borrowing a functional FPGA on a board as the basis for testing memory during prototype board bring-up and manufacturing has been implemented for years, but each such implementation has been developed by the board test provider and each test suite typically involves custom or functional development of test instruments and custom access protocols. The difficulty here is that the instruments embedded in the FPGAs are custom crafted for each board design with no, or limited, intended re-use. In some cases, developing the embedded instruments is as daunting a design task as developing the device’s functional firmware. In addition, the individual instruments that make up a multi-instrument tester embedded in an FPGA must be controlled and operated by design or test engineers. This would necessitate the development of an operating system for the embedded tester. Lastly, inserting and removing a multi-instrument tester from an FPGA must be a simple, straightforward process since most manufacturing board test engineers are typically not familiar with FPGA instrument insertion and other test-related operations. 16 EDN EUROPE | december 2012 www.edn-europe.com http://www.tmworld.com http://www.edn-europe.com/article.asp?articleid=5787 http://www.edn-europe.com/article.asp?articleid=5838 http://www.edn-europe.com

Table of Contents for the Digital Edition of EDNE December 2012

Cover
Contents
Texas Instruments Europe
Microchip
Digi-Key
Masthead
EDN comment
Pulse
Digi-Key
Baker’s Best
Embedded World 2013
Test & Measurement World
Rohde & Schwarz
Digi-Key
Squeezing the most from battery cells with a switched-mode pump
Signal integrity
Processor architectures : one to rule them all ?
Digi-Key
Mechatronics in Design
Advances in wireless speaker performance and technology
Design Ideas
Teardown; the ultimate Consumer Product ?
Product roundup
Tales from the Cube

EDNE December 2012