EDNE November 2012 - (Page 9)

eDn.comment By graham prophet, eDitor ,, Does your Design Need Non-Volatile Memory? Programmable prospects A s we reported in last month’s EDN Europe, and online, Altera has been discussing features of the programmable product it will release, at a later date, in 20-nm technology. This follows the now established pattern in the FPGA sector of making “technology announcements” (the underlying principles of what will become available) on a different cycle to the subsequent new-product introductions (namely, things you can actually place orders for). In general, in the past, EDN’s approach has been to focus on the latter, believing that our readers need to know about products you can actually design with on a realistic timetable: we have always been wary of, to revive that rather bizarre jargon of the 1990s, exercises in “opening the kimono”. However, in the case of the FPGA sector – or, to be realistic, Xilinx and Altera, as they so dominate that sector – we can make an exception: in part because their track record on making use, at the earliest possible time, of each new process geometry is good: and also, because those intentions are interesting in themselves, as they are often early in manifesting some of the important trends in the silicon domain. Accordingly, we have reported in the recent past on Xilinx’ intentions in 3D – in fact, 2½D, as the third dimension is currently limited to placing dice side-by-side on a separate silicon substrate; and on Altera’s intentions to place optical interconnect directly in the FPGA package. Both companies attest that they have actually built and delivered examples of both innovations – although, unless you happen to be working in one of the exotictechnology projects that need (and can afford) them, you won’t see either out “in the wild” for a while yet. Altera’s SVP of R&D, Bradley Howe, has been setting out his vision for the next generation of programmables at the leading edge. Referring back to the optical-interconnect aspect, he says that Altera will be able to stay in the electrical domain up to 40 Gbit/sec – for chipto-chip, and over very short distances – before the move to on-chip optical becomes compelling. What you’ll see interconnected in this way will be a heterogeneous (i.e., non-identical) collation of programmable logic, processors, and hard-coded (diffused) dedicated-function blocks. Also, naturally, on 2½D-moving-to-3D silicon packages. Configurability, or reconfiguration, will be at the level of assembling processorand block-level objects. Howe reiterates Altera’s faith in a C-based programming model, in which OpenCL will play a highly significant part. Which raises the question of tools: will the programmable sector be able to obtain effective design tools to enable that shift to a future in which stacked-die, through-silicon-via-connected technology becomes manageable? Problems of signal integrity and thermal modelling probably step up at least an order of magnitude compared to prior experience on a flat plane. Not to mention the issues of writing effective development tools for software that will run in a configurable hardware context. Will the third-party tool vendors (the EDA companies) ride to the rescue? They may not: they will find themselves in the familiar space of having an almost unlimited choice of challenging problems they might attack, but strictly finite budgets to carry out that development. For Xilinx and Altera the key may lie in getting the hardware out of the extreme-technology category as fast as possible – if they can “democratise” it and get the number of potential users growing as soon as possible, then thirdparties might see the potential returns begin to look attractive. And in these pages, we can start to report fascinating products that greater numbers of designers can access and exploit – and await the next round of mind-bending technology disclosures. Serial EEPROM, Serial SRAM, Serial Flash and Parallel Flash High Speed, Low Power and Fast Writes Superior Reliability www.edn-europe.com NOVEMBER 2012 | EDN EuropE 9 © Microchip Technology Inc. 2012 All Rights reserved DA122A/10.12 http://www.microchip.com/get/EUEDNEMEMORY http://www.edn-europe.com

Table of Contents for the Digital Edition of EDNE November 2012

Digi-Key
Cover
Agilent Technologies
Contents
International Rectifier
Microchip
Digi-Key
Masthead
EDN comment
Microchip
Pulse
Analog Devices
Maxim Integrated
Maxim Integrated
Texas Instruments
Silicon Laboratories
Test & Measurement World
FTDI
Digi-Key
Strategies for extending product reliability
Managing the 8- to 32-bit processor migration
PCIM
Pickering Interfaces
Mechatronics in Design
Baker's Best
Digi-Key
Emerson
30 years of DSP
Hirose
Vicor
The nuances of variable-frequency drives
Digi-Key
National Instruments
Volt’s battery-stack manager aids Chevy’s drive
Digi-Key
EDNE
Design Ideas
RS Components
RS Components
RS Components
Product Roundup
Tales from the Cube
RS Components

EDNE November 2012