The File - Feb 16 , 2009 - (Page 1)

India’s fortnightly focus on electronics design February 16-28, 2009 EDA solutions simplify analogue design By Sumit Arora Product Development Director CDBU Magma Design Automation ing and other proximity effects make it impossible to do prelayout sizing and have the chip work as expected once it is laid out. Circuit designers now need Analogue design, by nature, is complex and non-linear. Despite advances in computing and extensive research, the EDA industry has up to now failed to develop an analogue design solution that works on varied circuits and provides major productivity improvements to analogue designers. Traditional manual, mundane and time-consuming approaches must be replaced with new technology that offers higher levels of automation. As designs move to smaller geometries, even seemingly simple tasks like sizing are getting more complicated. At 65 nm and below, well-spacing, poly-spac- to consider placement of the devices and the effect of layout parasitic earlier in the design flow. A lot more information needs to pass between the layout engineer and circuit designer. There is an analogy from the digital world—in the late nineties and early 2000, physically aware synthesis, wherein the synthesis tool performs rough placement and global routing, was developed to reduce iterations. Analogue circuit designers may soon have to do the same during sizing to avoid iterations. Arora: The need for improvements in analogue design increases as SoCs incorporate both analogue and digital circuitry. We need a tool that removes the boundary between the two. Necessary improvements The new technology has to turn the art of analogue design to a science. We need tools that capture the design intent, which is not restricted to layout constraints but includes the actual electrical behaviour. We need analysis tools that help map a particular topology to different specifications, different foundries and even different processes without requiring the design to be re-analysed from scratch. This technology cannot be based on traditional time-consuming simulations with limited capacity, but must still be as accurate as a simulation. Plus, they need to optimise across PVT corners and do so in realistic time frames. Analogue synthesis may still be black magic but porting, optimisation and exploration of a known topology should not be, if it has been analysed once. We need to invest in automated, model-based analogue design techniques that allow us to develop soft-analogue IP that is easily reusable. continued on page Understand audio protocols, standards By Aseem Vasudev DSP Applications Manager Analog Devices India Pvt Ltd Inside In Focus 4 5 AFEs conquer ultrasound system design challenges Auto-detect peripherals in portables Audio technology has demonstrated tremendous advancement over the last few years, especially, in the home entertainment and car audio markets. The traditional four-speaker stereo system in cars is being replaced by the multichannel multi-speaker audio system. In India, televisions with a two-speaker stereo system have now been replaced with home theatre systems with multi-channel 5.1. The challenge in audio design nowadays is to emulate real life sounds and deliver them through various audio devices. Sound can come from any direction and our brain can actually compute and sense the origin of the sound. For instance, when a fighter plane flies from one point to the other, the sound emerging from it actu- ally moves through almost infinite points of origin in reality. However, we cannot have infinite speakers to replicate such audio experience. With multi-channel, multispeaker systems and a sophisticated audio algorithm, an audio system can almost emulate real life sounds. These complex audio systems use ASICs or DSPs to decode the encoded multi-channel audio and run various post processing algorithms. More channels mean increased storage and bandwidth requirement. Audio data compression techniques are then used to encode and reduce the size continued on page Events 8 NCCN 2009, IETF 2009, COMPONEX NEPCON 2009, Geomatrix ‘09, NCICT 2009 Sponsors 3 National Semiconductor www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/synthesis+tool.HTM?ClickFromNewsletter_090216 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/synthesis+tool.HTM?ClickFromNewsletter_090216 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/model~%40~based+design.HTM?ClickFromNewsletter_090216 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/65nm.HTM?ClickFromNewsletter_090216 http://www.eetindia.co.in/SEARCH/SUMMARY/new-products/RELEVANCE/multi~%40~channel.HTM?ClickFromNewsletter_090216 http://www.eetindia.co.in/SEARCH/SUMMARY/new-products/RELEVANCE/multi~%40~channel.HTM?ClickFromNewsletter_090216 http://www.embeddeddesignindia.co.in/SEARCH/SUMMARY/technical-articles/asic.HTM?ClickFromNewsletter_090216 http://www.embeddeddesignindia.co.in/SEARCH/SUMMARY/technical-articles/dsp.HTM?ClickFromNewsletter_090216 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090216_GS01.htm http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090216_EETI02.htm

Table of Contents for the Digital Edition of The File - Feb 16 , 2009

The File - Feb 16 , 2009