The File - March 16 , 2009 - (Page 1)

India’s fortnightly focus on electronics design March 16-31, 2009 Automate IP process migration By K. T. Moore Senior Director, Business Development Custom Design Business Unit Magma Design Automation Complexity and digital design are conspiring to drive a strong demand for advances in analogue electronics, creating a need for reusable and portable analogue intellectual property (IP). Remark ably, no ef f icient means of capturing or transferring analogue designers’ intent is available today. Developing reusable analogue IP will allow designers to build differentiated products fast and more cost effectively. It could help accelerate the adoption of newer process technologies, enable the creation of large libraries of analogue IP and give companies higher return on investments. IP reuse methodologies are available for digital blocks because of the well-structured and cell-based design characteristics. Automating the analogue IP process migration has been much Moore: Without automation, designers have to manually redesign the SoC’s analogue IP portion when migrating to a different process technology. more difficult because analogue design is far less standardised and far more irregular. Development is difficult because analogue and mixed-signal designs are prone to multiple design iterations and process sensitivities. Even with a well-defined standard, modifications may be needed. While there have been several attempts to develop an analogue-based IP reuse methodology, design teams ultimately rely on techniques that take hours of brute-force simulation and manual effort. This limits the size of the analogue IP content that can be ported or optimised to a new foundry or process/technology node. Maintaining accuracy, power, area or performance per the design specification has been difficult as well. Finally, digital designs and IP are regularly implemented in 32nm processes. Conversely, most analogue IP has remained at 0.25um and 0.18um, making the integration of analogue blocks difficult, time consuming and costly. The need for automation Without an automated methodology, analogue designers are forced to manually redesign the analogue IP portion of the system-on-chip (SoC) each time it is migrated from one process technology to another—an unacceptable situation. What is needed is a new design methodology that abstracts design knowledge, encourages reuse, performs complex computation over hundreds of design scenarios for the designer and integrates both electrical and physical design. continued on page Eliminate substrate coupling in MS SoCs By Brajesh Heda Lead Engineer Cadence Design Systems, India Inside Trends 2 4 Emulation bridges HW/SW verification Techonomic trends drive verification Over the past quarter century, the driving factors for the semiconductor industry are cost, power, size and performance. ‘On-chip integration’ seems to be the only buzzword as it is touted as the only way to meet these critical factors. Over time, Moore’s law and its derivatives have successfully proven this. Shrinkage in process technology has been of great help in meeting the demands in cost, power, size and performance. However, designers should also consider the complicated trade-offs when shrinking chip sizes. SoCs for wireless apps The strong demand for wireless and telecommunication applications is driving tighter integration of multiple heterogeneous com- ponents—such as front-end RF circuits, mixed signal (MS) circuits and high speed digital system— on a single system-on-chip (SoC). Digital and analogue signals are different in many ways. They have different signal representation (discrete vs. continuous) and simulation paradigms, and separate time point synchronisation. These differences cause difficulties in integrating digital and analogue domains on a single chip. Some of the problems can be tackled using verification techniques, some can be addressed at the flow level, while few can be solved during continued on page In Focus 6 Improve SSTA library characterisation Events 5 NCVESCOM ‘09, NCOCN ‘09, Energy World Show 09 Sponsors 3 National Semiconductor www.eetindia.com http://www.eetindia.co.in/STATIC/REDIRECT/EETI03B_090316_p1_survey.htm http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/IP+reuse.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/industry-news/analogue+IP.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/industry-news/analogue+IP.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/mixed~%40~signal.HTM?TheFile_090316 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090316_GS01.htm http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090316_EETI02.htm

Table of Contents for the Digital Edition of The File - March 16 , 2009

The File - March 16 , 2009