The File - March 16 , 2009 - (Page 4) Trends Techonomic trends drive verification By Bradley Geden Product Marketing Manager AMS Circuit Simulation Synopsys, Inc. The level of integration that designers can achieve today is staggering. Pick up any datasheet targeting consumer, networking or mobile applications, and you will find ICs that contain a number of micro, graphics and digital signal processors, megabytes of memory, high-end ADCs, power management circuitry, RF transceivers and the complete alphabet of high-speed serial I/O. The incorporation of system-level functionality requires design teams to develop system-level expertise in addition to covering a broad spectrum of IC design disciplines such as custom digital, analogue, mixed-signal, memory and RF. For each discipline, IC simulation technologies have evolved to verify and characterise individual blocks. Proving that these blocks meet specifications across a growing number of process corners is only a small part of the verification process. Design teams also need to understand how the integrated blocks impact the performance of their neighbours on the same IC. To reduce power consumption, these blocks are monitored and regulated by a complex power management scheme requiring full-chip transistor-level simulation to verify functionality and identify circuitry violating power limits. Time-to-market pressure and the high cost of re-spins necessitate predictable AMS verification methodologies and IC simulation technologies that cover the complete spectrum of IC design disciplines. These “techonomic” challenges, a unique combination of technology and economic trends, are driving the AMS verification needs. The number of possible process corners per operating mode is increasing steadily, yet corners alone do not tell the whole story. In order to prove that a design will deliver high yields, it must undergo extensive statistical analysis to minimise sensitivity to process variation and noise. Process variation is nothing new, but the degree to which parameters vary is growing. Designers are adopting digitally controlled analogue design methods to monitor and fine-tune circuit performance after fabrication to reduce the impact of process variation. Reliability is another factor impacting long-term yield. Technology factors influencing reliability include electro-migration, IR-drop and MOS ageing effects such as hot carrier injection and negativebias temperature instability. None set of electrical rules that require automated checking of every device during simulation. The sheer number of SPICE accurate simulations that must be run to adequately account for the impact of these trends can be overwhelming. Add to that the growth in design size and the increasing number of post-layout parasitic elements, and designers face the inevitable situation of making compromises, delaying schedules or taping-out with reduced confidence. Do more on EE Times India Ask the author Share article Say more • Discuss: Verification challenges Read related articles • Verification beyond base classes • Build OCP verification components • Accelerating verification closure for complex SoCs, IPs Geden: ‘Techonomic’ challenges are a combination of technology and economic trends driving the AMS verification needs of IC design teams. of these factors are new, but the role that they play is growing due in part to increases in the copper surface area, higher electric fields across gate oxides, higher temperatures due to increased power dissipation and less headroom between VTH and VG. In addition to power nets, signal nets must be analysed for EM & IR-drop, such as clock, amplifier outputs, etc. Nanometre devices have an increasing number of restrictions on how they can be operated. For example, low-VT devices have restrictions on VGS. These restrictions are defined in a Nanometre trends Designers must be confident that a circuit will meet specifications over a broad range of process, voltage and temperature corners. Power management Process engineers do what they can to reduce leakage power from a materials and processing perspective. Battery-powered applications demand lower power, and designers are employing a number of complex power management techniques. Power gating, multi-VT and dynamic voltage scaling are a few examples of strategies employed to reduce power consumption. These strategies must be centrally managed by a complex power management unit. A modern AMS era system-on-chip has many different modes of operation that must be individually verified to ensure that blocks are powered up and down with the correct supplies and in the correct state. This typically requires long transient simulations on the order of days or weeks. Power management verification needs to include checks that monitor when individual blocks are powered down so that no leakage power exists. Designers must check for correct power supply hook-up and confirm that no wasted DC paths exist. These additional tasks are time consuming and difficult to verify with simulation alone. A solution that can natively perform these checks during transient simulation is needed. Product life-cycle costs Keeping product life-cycle costs under control is an everyday economic reality facing semi- conductor companies. The price of a typical mask set for 45nm and below is a significant investment. Ensuring first-pass success is a critical AMS verification objective. Design teams need a predictable AMS verification methodology that will guarantee confidence levels in the shortest possible verification time. Digital verification has evolved into a formalised verification methodology utilising SystemVerilog assertions. Research is underway to define AMS extensions to SystemVerilog as well as the analogue equivalent of assertions. The prevailing theory on analogue assertions is that a combination of signal monitors, probes and native circuit checks is needed to define an assertion in the AMS domain. New solution required Designers need a comprehensive circuit simulation solution, from RTL to transistor level, that provides a combination of best-in-class technologies for high performance full-chip verification. A number of challenges dictate the need for a comprehensive set of static and dynamic native circuit checks that can monitor the design for violations of electrical rules. The complete circuit simulation solution needs to be supported by an AMS verification methodology built on analogue assertions to reduce product life-cycle costs. ■ 4 EE Times-India | March 16-31, 2009 | www.eetindia.com http://forum.eetindia.co.in/FORUM_POST_1000039193_1200092210_0.HTM?TheFile_090316 http://www.embeddeddesignindia.co.in/SEARCH/SUMMARY/technical-articles/DSP.HTM?TheFile_090316 http://www.eetindia.co.in/ART_8800564010_1800000_TA_fea8298e.HTM?TheFile_090316 http://www.embeddeddesignindia.co.in/SEARCH/SUMMARY/technical-articles/DSP.HTM?TheFile_090316 http://www.eetindia.co.in/ART_8800563071_1800000_TA_f407b1d1.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/ADC.HTM?TheFile_090316 http://www.eetindia.co.in/ART_8800549661_1800000_TA_46335285.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/serial+I%5E%40%5EO.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/SystemVerilog.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/RTL.HTM?TheFile_090316 http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_090316_EETI02.htm
For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.