The File - March 16 , 2009 - (Page 5) Trends Automate IP process migration continued from page Events NCVESCOM ‘09 Requirements for this effective IP reuse methodology include accelerating process migration with a full-chip, mixedsignal and analogue design, analysis and verification platform that tightly integrates mixed-signal and digital implementation, circuit simulation, transistor-level extraction and verification. Such a tool should be able to represent analogue functionality at a high-level of abstraction and have the abilit y to use these representations to generate transistor-level equivalents. The tool should automatically optimise analogue circuits and automatically place-and-route these analogue circuits. In traditional f lows, chip finishing—where digital and analogue blocks of a design are placed and routed together—is a manual task. This next-generation platform must offer automation from start to the chip finishing capabilities. It should include an integrated simulation environment to provide a level of efficiency in the analogue design domain that is similar to that of the digital domain. It should also leverage a modelbased approach to ensure better performance, to identify process, voltage and temperature (PVT) corner cases, and to reduce power and area. The ability to reuse analogue design functions in electronic devices is one of the most underdeveloped areas in electronics design, offering an immediate need for more automated meth- Do more on EE Times India Ask the author Share article Read related articles • Magma acquires Sabio to beef up mixed-signal portfolio • Verification IP reuse for complex networking ASICs • Low power design for analogue/mixed-signal IP Mar. 26-27, 2009 Aarupadai Veedu Inst. of Tech., Chennai The 2nd National Conference on VLSI, Embedded Systems, Signal Processing and Communication Technologies aims to bring together academicians, research scholars, professionals and industry experts on a common platform to exchange findings and technical ideas in these fields. Inquire here or go to event website. NCOCN ‘09 Mar. 27, 2009 VAST, Thrissur, Kerala ods to capture the analogue designer’s intent. With more efficient analogue IP reuse methodologies, companies could accelerate adoption of newer process technologies, and create and use more components from analogue IP libraries. ■ The National Conference on Communication Networks will feature research papers related to advanced developments in the field of electronics and communications. International experts will deliver keynote lectures. Go to website or inquire direct. Energy World Show 09 Mar. 20-22, 2009 University Ground, Ahmedabad, Gujarat Emulation bridges HW/SW verification continued from page approach based on multiple abstraction levels. They can track a design problem across the boundary between the embedded software and the underlying hardware to determine whether it is a software or a hardware problem. To be effective, emulation must have a software-aware debugging environment to track a bug in hardware coming from the software debugger. Traditional emulation systems are not effective because they execute at sub-megahertz speeds—which is unacceptable for software developers—and do not have the software-aware debugging environment. Prototyping systems are fast but lack the full visibility into the design, mandatory for hardware debugging or the software-aware debugging environment, also unacceptable to software developers. System-level validation— traditionally, the purview of in-circuit emulation (ICE)—is going through a transformation, adopting co-emulation and transaction-level methodologies, eliminating complex hardware targets in favour of flexible programmable test benches. Early versions of emulators used an ICE mode that connected real target devices to the behaviour of the system under the presumption that the results would be accurate. Unfortunately, the emulated design ran at a fraction of the speed of the actual silicon, speed bridges had to be inserted to adapt traffic between the live devices running at real speed and the design executed at lower speed. The different speeds broke the timing relationships between the test environment and the emulated design, preventing the ability to test many critical scenarios. The design team was convinced that the design was functional, only to discover that problems remained after tape-out. By using existing off-the-shelf transactors, design teams can build a complete environment for most standard SoC applications. Transactors are differentiated from other reusable verification IP described via a hardware description language (HDL) by Do more on EE Times India Ask the author Share article Read related articles • Emulation wins over FPGA prototyping • Accelerate functional verification • Analogue verification opportunities Energy World focuses on recent trends and developments in the power, energy and instrumentation sector. It will be attended by professionals working on renewable energy, instrumentation, test and measurement instruments, and electrical/electronics components and accessories. Learn more from website or inquire. More eeEvents… their speed. Once in emulation, a design is capable of processing millions of requests per second, much faster than what a software simulator can handle. With more speed, there is no need to break the main user function of the device into smaller elements. Emulation provides an all-inone system for hardware debugging and embedded software validation. Hardware designers and software developers can share the same system and design representations, and work together to debug hardware/ software interactions. Design teams in India and Synopsys to dominate EDA market? Sharat Kaul of Synopsys said, “I can understand our customers’ views on having choices for vendors, but vendor consolidation makes business sense during these tough economic times…” elsewhere are adopting new emulation systems as an essential element of their verification and validation strategy because of their proven effectiveness, attractive pricing and ability to bridge hardware and software design. ■ 5 EE Times-India | March 16-31, 2009 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/verification.HTM?TheFile_090316 http://www.eetindia.co.in/ART_8800507540_1800000_NT_52821410.HTM?TheFile_090316 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013500&eventLocId=1000001460&method=inquiryEnter&eventType=EE?TheFile_090316 http://www.eetindia.co.in/ART_8800544447_1800000_TA_cd9b6c21.HTM?TheFile_090316 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013500&eventLocId=1000001460&method=inquiryEnter&eventType=EE?TheFile_090316 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090316_NCVESCOM.htm http://www.eetindia.co.in/ART_8800510150_1800004_TA_0470dbde.HTM?TheFile_090316 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090316_NCOCN.htm http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013498&eventLocId=1000001458&method=inquiryEnter&eventType=EE?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/new-products/IP+library.HTM?TheFile_090316 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090316_EnerWorld.htm http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013496&eventLocId=1000001456&method=inquiryEnter&eventType=EE?TheFile_090316 http://www.eetindia.co.in/ART_8800497522_1800000_TA_055dcf7a.HTM?TheFile_090316 http://www.eetindia.co.in/EVENT_DISPLAY_EE.HTM?TheFile_090316 http://www.eetindia.co.in/ART_8800553888_1800000_TA_276868b1.HTM?TheFile_090316 http://www.eetindia.co.in/ART_8800557661_1800000_TA_d341b80c.HTM?TheFile_090316 http://forum.eetindia.co.in/FORUM_POST_1000039165_1200108023_0.HTM?TheFile_090316 http://forum.eetindia.co.in/?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/HDL.HTM?TheFile_090316 http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_090316_EETI02.htm
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