The File - March 16 , 2009 - (Page 6) In Focus | Analogue-mixed signal design Improve SSTA library characterisation By Pramod T Senior Manager Product Development Magma Design Automation int racell . delay/slew can be represented as: Do more on EE Times India ∆ Dint racell = C1 ∆P1T 1 + C1 ∆P1T 2 + C 2 ∆P 2 T 1 + C 2 ∆P 2 T 2 + 2 1 C1, C2, etc., can be determined ∆ Dint racell C1 ∆P1T 1 by varying the process =param- + C12 ∆P1T 2 + C 21 ∆P 2T 1 + C 2 ∆P 2T 2 + Ask the author eters, measuring the correspond- represents variation of process ing delay/slew variation and then parameter Pi from nominal value Share article ij doing a curve fit. This can be quite ∆P T for transistor Tj . Cij is the expensive in terms of runtime corresponding sensitivity. Once Say more because, for a given process, there all the sensitivities are identified, • Comment on this article can be tens of process parameters the intra-cell standard deviation which vary statistically. Finding can be determined analytically. Read related articles can be even more time consum- Even with this model, a few huning. A Monte Carlo simulation dred sensitivity coefficients must • Signoff for manufacturability can be done by varying process be found for bigger cells. Each • Know the truth behind static analysis parameters. Note that for intra-cell coefficient here corresponds to a • Effectively use a static analysis variation, if there is one process process parameter for a particular tool parameter per transistor which transistor in the cell. If there are varies, there are as many random N transistors and M process pavariables as the number of tran- rameters, this translates to N*M sistors in the cell. So, the cost of sensitivity coefficients. tween the characterisation sysdoing a Monte Carlo simulation Not all transistors actively tem and the SPICE simulator is file increases as the number of transis- participate in the transition for based. Significant improvement tors in a cell increases. a timing arc. So, it is safe to ig- is possible if the simulator can be So, it is evident that some inno- nore coefficients corresponding tightly integrated with the charvative methods are needed to do to those transistors. However, acterisation system so that the cell characterisation for SSTA while identifying those transistors is communication is through applikeeping runtime under control. not easy. A characterisation tool cation programming interfaces. In cell characterisation, the tim- needs to automatically locate This helps in two ways. One, it ing behaviour of a cell is tabulated such transistors. It is also helpful if helps to avoid the overhead asacross a range of input slew-out- a slew-load dependent screening sociated with calling an external put load values. It is observed that is done, as in the case of inter-cell simulator. Two, if it is integrated sensitivity to process parameter variations. In the end, there is a with an ultra-fast simulator, it variation of timing behaviour of a much smaller equation. Once can provide a 3X to 10X runtime cell is not similar across input slew- the equation is derived, standard improvement. With innovative output load variation for an arc. At deviation of delay/slew can be techniques and integration to a given slew-load combination, determined analytically. a SPICE simulator, it is possible timing behaviour is more sensitive Traditional cell characterisa- to do SSTA characterisation in a to some parameters than to other tion systems are implemented as matter of a few hours. parameters. If “dominant param- a wrapper over a SPICE simulator. Read the full article to know eters” can be identified, charac- This model has a huge overhead the other variations in SSTA terisation time can be reduced because the communication be- models. ■ by varying only those parameters which are dominant. The characBack to the Blackboard terisation tool needs to be able to identify the dominant parameters for each slew-load. This will reduce the number of sensitivities and improve SSTA characterisation runtime significantly. Intra-cell characterisation is more time-consuming than inint racell ter-cell characterisation because the number of random variables increases as the size of the cell increases. Embedding a Monte Basic building blocks in analogue ICs Carlo simulation for each slewHere’s a lecture that focuses on current mirrors as a fundamental load combination is not a feasible aspect of analogue ICs. Prof. K.Radhakrishna Rao from Department solution because it is expensive. of Electrical Engineering, IIT Madras, conducted this lecture. So instead of doing a Monte Carlo This video lecture on EE Times India is brought to you by the National Programme on Technology Enhanced Learning, an initiative by seven IITs and the IISc for creating course contents in engineering simulation an analytical solution and science. This programme is funded by the Ministry of Human Resource and Development. can be used. Intra-cell variation σ D = Dnom + C1 ∆P1 + C 2 ∆P2 + + σ As process feature size shrinks, the need for statistical static timing analysis (SSTA) also grows. Traditional corner-based timing analysis is not enough to predict timing behaviour accurately in smaller geometry nodes. To scale below the 65-nanometer node, more accurate timing analysis is needed. SSTA tools need to know how cells respond to variation in process parameter values. Several EDA companies have developed their own SSTA tools and their own format in which this information can be stored in a cell library. Generating these models in a reasonable timeframe for a standard-cell library is a challenge. Model generation requires several simulations of the same cell where each simulation corresponds to different process parameter combinations. In this way the response of the cell to variation in these process parameters can be assessed. A brute force method of doing this will take weeks. A better method of doing cell characterisation for SSTA that significantly reduces runtime is needed. This method must include innovative techniques and tighter integration with a SPICE simulator to enable SSTA characterisation in a few hours. From a cell characterisation point of view there can be two types of process parameter variation: inter-cell and intra-cell. The timing behaviour of a cell taking into account process parameter variations can be represented D = Dnom + C1 ∆P1 + C 2 ∆P2 + + σ as: int racell D nom is the nominal timing behaviour (delay/slew). ∆P1 ∆ P2 , etc. are process parameter variations from the nominal value. σ int racell represents variation due to intra-cell parameter variation. The standard-cell library should contain the sensitivities, C1 C2 etc. and standard deviation of 6 EE Times-India | March 16-31, 2009 | www.eetindia.com http://www.eetindia.co.in/article/sendInquiry.do?articleId=8800565222&catId=1800000?TheFile090316 http://www.eetindia.co.in/ART_8800565222_1800000_TA_a978bf6d.HTM?TheFile_090316#cnt http://www.eetindia.co.in/ART_8800553889_1800000_TA_f6a6ab3e.HTM?TheFile_090316 http://www.embeddeddesignindia.co.in/ART_8800563494_2800006_TA_95a2e37c.HTM?TheFile_090316 http://www.embeddeddesignindia.co.in/ART_8800562757_2800006_TA_e59e19e9.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/RELEVANCE/EDA.HTM?TheFile090316 http://www.powerdesignindia.co.in/SEARCH/SUMMARY/technical-articles/transistor.HTM?TheFile090316 http://www.eetindia.co.in/ART_8800565222_1800000_TA_a978bf6d.HTM?TheFile_090316 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/SPICE.HTM?TheFile090316 http://www.eetindia.co.in/STATIC/VIDEO/Analog_ICs_Lecture1_20090106TheFileMarB.HTM?TheFile_090316 http://www.eetindia.co.in/STATIC/VIDEO/Analog_ICs_Lecture1_20090106TheFileMarB.HTM?TheFile_090316 http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_090316_EETI02.htm
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