Instrumentation & Measurement Magazine 23-5 - 23

Fig. 4. An Eye Diagram and its Characteristics [13], used with permission.

documentation, it is called a test program set (TPS). The TPS,
developed a priori by a test engineer to provide a complete
test, is repeated for each UUT to be tested. For low speed applications, this approach has been quite effective. Over the
years, the cost of the test instruments and ATE hardware have
been reduced, while the complexity of the test programs has
actually increased much more. This has resulted in an increase in the net overall test cost. An important cost driver is
the need to develop a unique test program for each UUT design and each UUT has become ever more complex. Another
impediment is that the test instruments must remain general purpose, which requires that test instruments include
many parameters with wide ranges so that they can be of use
to as many different circuits as possible. Such instrument designs are typically restricted to the low-speed domain (under
10 MHz) because cabling length between the instruments and
the UUT is substantial and usually several instruments must
be placed in an ATE rack.

Fig. 5b indicates that
SIs can be created to mimic
general-purpose test instruments. We believe that
we can replace the rack of
general-purpose test instruments with a software
database of SIs stored in
the memory of a single
FPGA development board.
Additionally, SIs can be developed with enhanced
functionality unrealizable
in general-purpose test instruments. For example,
the USB 3.0 SI performs all
the functions of a USB 3.0
controller and/or peripheral even though no such
test instrument presently exists on an ATE. To utilize a particular test instrument function as an SI, one simply loads a
particular bitstream that will configure the FPGA to behave as
the desired instrument. A library of many different SIs can be
assembled and maintained, allowing the FPGA to perform the
existing functions of a large size ATE as well as substantially
improved functionality, all on a much smaller footprint tester.
The SI tests can be run at the transceiver speed of the FPGA,
which in today's FPGAs exceeds 25 Gbps. This is more than
sufficient for testing most high-speed buses, such as the USB
3.0 shown on the figure, that transfers data at 5 Gbps. Moreover, the speed is scalable. As circuit technology allows for
higher speeds, higher speed FPGAs will have higher speed
transceivers.
A major advantage of the synthetic ATE is the availability
of many test instruments in a small footprint. This advantage is even more compelling when we consider that several
"copies" of an SI can be readily made without any additional

Fig. 5. Transitioning ATE Design from Traditional to Synthetic Instruments. (a) Current ATE Designs; (b) ATE and Test Set Designs Using Synthetic Instruments (SIs).
August 2020

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Instrumentation & Measurement Magazine 23-5

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