Instrumentation & Measurement Magazine 24-9 - 8

candidates produced at zero angle 480 m downstream the ATLAS
beam-collision point.
One of the most challenging searches requires distinguishing
two extremely energetic (~1 TeV) photons with ~200 μm
separation. For this purpose, FASER will be instrumented
with a pre-shower detector able to convert and measure separately
the two very collimated TeV photons by the energy
deposition in our monolithic pixels. In the present design, the
pre-shower will be made of 6 tungsten planes alternated to
planes of monolithic silicon pixel sensors in the SiGe BiCMOS
SG13G2 technology by IHP covering an area of 16×16 cm2
each. The sensors will have hexagonal pixels of 65 μm side
and a time resolution of 100 ps. The power consumption will
be 7 μW per channel, to stay safely below the power budget of
350 mW/cm2
.
The pixels are produced as deep n-wells and kept at the
amplifier supply voltage; a negative high-voltage (-200 V) is
applied to the boron-doped substrate. This solution requires
insulating all the electronics from the substrate using triple
wells and placing the front-end electronics directly inside the
pixels to minimize the amplifier input capacitance. IHP developed
for this project an isolated HBT that can be placed inside
a triple well that shows similar high-frequency performance
of their standard transistor.
The NMOS transistors,
as well as polysilicon resistors,
can be placed in
an insulated p-well inside
the pixel with a limited increase
in pixel capacitance,
while the PMOS transistors
are directly inside the sensitive
pixel n-well.
Fig. 3a shows the schematic
of the pixel and the
present implementation of
the front-end electronics.
In this case, polysilicon resistors
cannot be used to
apply the pixel bias, due to
the low ratio between resistance
and capacitance per
unit length. At the same
time, the pixel should be
biased at the front-end supply
voltage, to avoid body
effects on the preamplifier
PMOS load. The proposed
solution is using a PMOS in
triode configuration with
a dedicated bias setting its
dynamic resistance. The capacitive
coupling between
the pixel and the preamplifier
is done using the
junction capacitance of an
8
array of large area PMOS transistors. This configuration operates
up to a current of few nA, due to the saturation of the bias
component.
The active volume of the FASER monolithic pixel sensor
is produced in a 50 μm thick epitaxial layer with a resistivity
in the range from 200 Ωcm to 500 Ωcm on top of a heavily
doped substrate. This solution allows controlling the depletion
volume without excessively increasing the electric field
near the sensor surface. It also removes the necessity for a backside
implantation and the extreme die thinning that would
be required to operate this sensor at full depletion, with the
advantage of getting rid of the post-production stage on the
CMOS processed wafer. The inter-pixel region contains a
pstop implantation to guarantee the pixel-to-pixel insulation
without using a p-well. The choice of using the hexagonal pixels
(Fig. 3b) improves the resolution for the photon separation
measurement and, avoiding pixel edges with angles below 120
degrees, reduces the electric field near the chip surface.
To test the concept of this monolithic implementation,
first a small-size prototype chip (Fig. 4a) was produced in the
SG13G2 IHP process. The prototype had two matrices of hexagonal
pixels of 130 μm and 65 μm side. The electronics were
placed in separate n-wells from the pixels.
Fig. 3. (a) Schematic circuit of the FASER pixel and preamplifier; (b) Layout of the routing from the pixels to the digital
periphery for the monolithic implementation of the FASER chip.
IEEE Instrumentation & Measurement Magazine
December 2021

Instrumentation & Measurement Magazine 24-9

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