Instrumentation & Measurement Magazine 25-5 - 57

The maximum and minimum currents are determined by the
specifications of the power rail under test. Each CPU power
rail has a different specification depending on the functional
or logic block it powers. Static load currents are also applied
when generating the VR dc regulation and efficiency data.
Automation scripts are used to generate the VR efficiency
and dc load regulation plots by capturing the input and output
voltages and currents of the VR while sweeping the load
current.
For post-silicon validation, the CPU silicon die and its
package are connected to the socket on the motherboard via
a special designed interposer that has test points to measure
CPU current and voltages under various application
workloads [11]. These workloads can serve as benchmarks
to measure the CPU performance. During post-silicon validation,
the CPU is booted, and the workload applications
are loaded onto the booted system. These workload applications
stress various functional blocks of the CPU. When
the CPU is undergoing these stress validations tests, the
currents and voltages of the different CPU power rails are
measured to ensure that they are within the design specifications.
Other post-silicon validation measurements
include an ac impedance measurement called integrated
power supply frequency domain impedance meter (IFDIM)
[12]. This is integrated on the CPU die and provides a measurement
of the impedance profile of the PDN from the CPU
die to the VRM. During measurement, all logic activity on
the die is disabled and a clock signal is generated such that
the CPU current waveform is rectangular and can be decomposed
into various harmonics. The output of the IFDIM is
connected to an oscilloscope, which in Fast Fourier Transform
(FFT) mode can decompose the waveforms into the
first, third, and fifth harmonics. The PDN is a linear time
invariant system, and as such, the superposition principle
applies. The voltage measured will also contain these harmonics,
and the impedance can be calculated and extracted
over a wide range of frequencies.
Correlation
When accurate VRM and PDN models used in simulation
correlate well with their corresponding lab validation
measurements, the confidence for predicting server platform
power delivery behavior is enhanced. It also enables
iterative design parameter modifications without having
to redesign, wait for hardware, or physically make
those changes on the hardware to quickly perform 'what
if' scenarios with respect to maximum current change and
decoupling capacitance optimization. If correlation is not
established, the models cannot be used. In doing correlation,
there are many challenges that can arise. These include
limitations in VR models, where the VR models do not accurately
reflect their hardware measurements, limitations
in lab measurement tools, especially in the case of high di/
dt current events or very high currents or limitation in data
capturing tools, and parameter variations of different passive
components used on the platform, such as VR inductors
August 2022
and capacitors which can have a tolerance range due to
manufacturing variations and/or temperature.
VR models with linear controllers can be modeled using
the state space average VR behavioral models while VR models
with non-linear controllers use piecewise linear methods
to model the switching behavior of the VR. Correlating the VR
model used on a server platform is important as using a VR
model without first correlating can result in inaccurate CPU
transient performance predictions leading to insufficient decoupling
capacitors or an over design resulting in increased
costs. To validate the VR model, three phases are presented:
◗ The first phase is to correlate the VR models with their
evaluation boards (EVB) developed by VR vendors. The
parameters of the EVB PDN are extracted for use in a
circuit simulator with the VR controller model. Simulations
are performed using the same configuration used
during lab measurements, such as slew rate of the transient
load current, minimum and maximum load current
values, VR compensation tuning, capacitors and inductor
values. If there are discrepancies between the VR's performance
on the EVB and simulation, these discrepancies
need to be root caused, and the next phase cannot proceed
unless the discrepancies are resolved. Once there is good
correlation between the VR model and hardware, the next
phase can advance.
◗ The second phase is correlating the VR model with the
server PDN with different configuration parameters.
In this phase, the VR is tested with different configuration
files to ensure that the VR model was not specifically
tuned to correlate to the EVB under a certain specific and
unique condition. This configuration can be changing
the passive component values, VR tuning parameters,
or worst-case transient conditions. Once correlation is
determined in this phase and such that the VR model can
predict behavior similar to what is on the hardware, no
matter the configuration, the next phase can proceed.
◗ In the third phase, the VR model has been qualified to use
with the server platform PDN, and once this is achieved,
there is confidence in the VR model.
To correlate the server platform PDN, the flow chart shown
in Fig. 5 is followed and repeated until the platform PDN models
correlate adequately. This is with the assumption that the
VR model has been previously correlated. Once the server
platform transient lab measurements results are received,
the platform PDN is extracted and characterized using full
wave solvers and macromodeled to make it SPICE compatible,
i.e., conversion from scattering parameters into electrical
models. The simulation of the platform PDN and VR model is
performed using the same parameters used during lab validation.
These parameters include maximum and minimum CPU
load current, slew rate, and VR configuration parameters. The
aim is to make the simulation setup the same as the validation
setup.
Once this is achieved, the simulated results can be compared
with the validation results to determine if there are any
discrepancies. Any discrepancies noticed can be attributed
IEEE Instrumentation & Measurement Magazine
57

Instrumentation & Measurement Magazine 25-5

Table of Contents for the Digital Edition of Instrumentation & Measurement Magazine 25-5

Instrumentation & Measurement Magazine 25-5 - Cover1
Instrumentation & Measurement Magazine 25-5 - Cover2
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Instrumentation & Measurement Magazine 25-5 - Cover3
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