IEEE Instrumentation & Measurement - September 2023 - 14

edge arrives, propagated ISn is latched by D-type flip-flops
to store the output of the DEs. According to Fig. 2, two fine
measurements must be done. The first one is the time interval
between ISn rising edge and the subsequent clock rising
edge (Tn
()1). The next rising edge comprises from ISn falling
edge and the subsequent clock rising edge (Tn
on how far ISn was propagated, FM can be deduced. Therefore,
ISn width is the time to be measured (Wn) and can be
expressed as W C TT T
nn
nn
() ( )12≥
W C TT T T when TT . The component
that measures fine intervals (Tn
()1 and Tn
()2) is commonly
n = +(())× − +
referred to as the interpolator.
Detectors in PPE usually require hundreds or thousands
of readout channels to acquire complete information about
generated radiation [2]. Nevertheless, TDCs research usually
focuses on designing a highly efficient architecture for
time measurement in a single channel. Multichannel TDCs
usually employ a channel replication method, in which a
single-channel architecture is replicated until reaching the desired
number of channels, limited only by the target device
hardware resources [5]. This makes commissioning prototypelevel
systems challenging since only high-end devices contain
enough hardware resources. It is not yet clear how to develop
highly-resource-efficient multichannel systems. Furthermore,
to meet the particle identification requirement of next-generation
particle accelerators, the time resolution in these detectors
should preferably reach the picosecond level [6]. For this reason,
new methods must be developed to measure these times
in new experimental proposals.
Some state-of-the-art TDCs designs have been implemented
utilizing application-specific integrated circuits
(ASICs). They can get sub-picoseconds resolution employing
both digital and analog circuits (a complete review of these
techniques is presented in [7]). Nonetheless, implementing a
dedicated TDC on ASIC requires a relatively long development
time and specialized knowledge. Instead, in recent years,
time interval measurements (TIMs) have been performed using
fully digital strategies using field programmable gate
arrays (FPGAs). An FPGA solution is often considered a promising
alternative because of its flexibility, faster development
phase, lower implementation cost, and competitive performance
compared to ASIC.
The rest of this document presents a review of implementation
strategies to measure time intervals using FPGA-based
TDCs with potential application to multichannel scenarios.
For this review, the classic methods to perform the FM are
mentioned since this part is the one that represents the most
significant challenge and for which researchers have proposed
more meaningful solutions. Subsequently, the potential areas
of research that promote the inclusion of current ideas in multichannel
TDCs are discussed since this represents a field hardly
explored so far.
Representative TDC Components
A representation of a single channel TDC is presented in
Fig. 3. This architecture represents the general trend for TIMs.
14
1 21( ) ()
n = +(())× −+1 21( ) () when TT and
nn +
nn
() ( )12<
()2). Depending
Clk
Fig. 3. Representative components for single channel TDCs hardware
architecture.
It is composed of a coarse counter that computes the number
of clock cycles in which the IS is high. This way, an approximate
measurement of W or P is achieved, having a resolution
of T
= F1/
IS
Fine measurement
Capture Module
Coarse measurement
Postprocessing
and a measurement range of 2n, where n is the number
of counter bits. TDL designs operate at frequencies F in
ranges 250 MHz up to 600 MHz (T in the range of 1.66 ns to
4 ns). By only using CC, measuring time intervals in the order
of picoseconds is impossible. Additional components such
as an interpolator, a pulse shaper (PS), and postprocessing
(composed of an encoder and a calibration stage) are used to
improve this resolution beyond nanoseconds.
Tapped Delay Line as Interpolator
The most popular topology for FM in FPGA-based TDCs is
the tapped delay line (TDL) (presented in Fig. 4a), which is
intended to perform propagations of IS (in case there is no
PS) within one clock cycle. The TDL-based TDCs use DEs for
quantifiable propagation time. Ideally, the delay of all DEs in
TDL should be equivalent to T. Thus, the clock frequency determines
the minimum TDL length. When TDL receives IS, it
is possible to obtain a picoseconds-resolution measurement
based on how far IS was propagated. The average propagation
delay of each DE determines the TDC resolution, which
typically is on the order of picoseconds. The propagated signal
is latched by D-type Flip Flop in the capture module on every
rising edge of the clock signal, thereby obtaining the TDL
status. The physical implementation of DE depends on the selected
FPGA technology. In the case of Altera FPGA, adders in
Adaptive Logic Module (ALM) are used due to their fast carry
connections (Fig. 4b). For Xilinx technology, slices provide cascadable
multiplexers whose output can be captured directly or
indirectly through an OR gate (Fig. 4c). Noteworthy is that the
goal is to use short and homogeneous connections that provide
the least possible propagation time.
Pulse Shaper
When IS propagates in TDL, the achievable resolution is
equivalent to the average propagation of DEs. This resolution
can be improved beyond this intrinsic resolution by
using a PS; a train of pulses is fed into TDL once the rising
edge of the input signal arrives. The clock signal latches
the TDL status out. The sampled code contains alternating
sequences of high and low logic states. Thus, an encoder performs
multiple measurements to determine how far these
IEEE Instrumentation & Measurement Magazine
September 2023
Pulse
Shaper
Encoder
Calibration
Final Measure

IEEE Instrumentation & Measurement - September 2023

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