IEEE Instrumentation & Measurement - September 2023 - 18

Table 2 - Obtained performance in recently reported FPGA-based TDCs
Work
Parsakordasiabi
2021 [3]
Kuang 2018 [13]
Zhang 2022 [11]
Zhu 2021 [10]
Cao 2018 [17]
Garzetti 2021 [16]
Zhang 2021 [18]
Jiao 2021 [5]
Szplet 2021 [19]
Song 2020 [20]
Tang 2021 [21]
Technology
Artix-7
XC7A200T
Kintex-7
XC7K325T
Zynq-7020
XC7Z020
Virtex-7
XC7VX485T
Cyclone-IV
EP4CE115
Artix-7 200T
Kintex-7
XC7K325T
Virtex-6
Virtex-7
XC7VX485T
Cyclone 10 LP
Kintex-7
XC7K325T
22.2
≈ 3
17.4
2.03
45
0.366
43
9
13
8.8
15
(single shoot precision); OP (Overall precision); MC (Multichannel);
and HP (High-Performance). In the case of the range
metric, there is no indicator of how good (or poor) this result is
due to the fact that it is given mainly by the target application.
Differential Non-Linearity (DNL) and Integral Non-Linearity
(INL) are indicators of linearity. For these results, minimizing
the range as narrow as possible, besides having a zero mean,
is sought. Finally, the dead time represents the postprocessing
component processing time, which falls directly on the number
of samples per second that can be performed, typically
quantified in Mega Samples per second (MS/s). The trend is
to find a suitable coding method that processes the TDL status
in the order of two or three clock cycles. This would allow
sampling capacities greater than 100 MS/s. For Table 2 and
Table 3, the values containing the symbols ≈, >, <, or - are used
because the paper does not provide explicit information on
this result.
Table 3 shows a summary of resource utilization (in terms
of Luts, FFs, and DSPs) besides power and the Maximum Theoretical
number of Channels (MTC) for those papers presented
in Table 2. Only some authors report resource utilization; this
is because results such as resolution, precision, and linearity
are the main research concerns. Nevertheless, to know the
potential of the proposals in a multichannel scenario, it is important
to see the relationship between performance and the
employed resources. It is observed that a greater number of
channels is achieved either through architectures based on a
single TDL or with the implementation on high-end devices.
Yet, additional studies are necessary to determine the best
18
Resolution
LSB (ps)
Dead
Precision (ps) Range DNL (LSB)
26.04 (SSP)
5.85 (SSP) 5.76
(OP)
18 (SSP) 19
(OP)
2.8
18 (SSP)
>18(OP)
8 (SSP)
34 (OP-MC) 17
(OP-HP)
6.2 (SSP)
<21
-
-
INL (LSB)
262.14 µs [-0.953, 1.185] [-2.750, 1.238]
0-30 ns
47.9 ms
(24b)
7 s (32b)
0-7.5 ns
10.3 s
-
-
3.4 ns
-
-
-
[-0.90, 1.67]
[-0.89, 6.2]
[-0.5, 0.13]
<0.683
(-0.98, 0.08)
[-0.9, 3.66]
-
≈ [-0.81/ 1.20]
[-3.18, 3.46]
≈ (-8, 9.33)
[-1.90, 3.31]
[-3.2, 22.3]
[-0.48, 0.37]
<6.8
(-1, 0.97)
[-4.74, 26.01]
-
-
[-4.65, 9.59]
time (ns) /
MS/s
8/125
22/45.45
5.882/170
3.33/300
13.3/75
5/150
50/20
5/150
-
-
-
strategy to achieve a greater number of channels without sacrificing
the performance in each TDC.
In addition to the TDL-based architectures, other variants
have proven to achieve competitive results: Vernier Delay Line
(VDL) and multiple Clock Phases (MCP) methods. VDL uses
two clock signals of similar frequencies to measure the time
interval. The resolution of Vernier TDCs is determined by the
period difference between the two oscillators. This method
implies that a higher resolution normally leads to a longer
measurement dead time, as more oscillation cycles are needed
to measure the time interval [10]. Thus, it may be inadequate
for high-speed measurements in systems requiring many measurement
channels. The MCP method generates multiple
clock signals with different clock phases each. The idea is that
n clocks with different phases each sample the input signal in
each measurement channel. This technique makes it difficult to
obtain a high resolution because the number of phases that can
be obtained is usually not greater than 16 when high-frequency
clocks are generated. Hence, the best achievable resolution in
this method is limited to the Voltage Controlled Oscillator frequency
(fVCO) of the Phase Locked Loop (PLL) component,
which can deliver a minimum clock phase of (/ )18fVCO × for
a maximum oscillation frequency of around 1.6 GHz [3], [11].
The current research on developing new architectures for
TDC is mainly focused on improving either performance or reducing
resource utilization. Nonetheless, these proposals are
thought of as general-purpose instruments, so they are not designed
for PPE. In research stages, particularly in the academic
field, prototype-level systems are usually limited to the use of
IEEE Instrumentation & Measurement Magazine
September 2023

IEEE Instrumentation & Measurement - September 2023

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