Evaluation Engineering - 18

AUTOMATED TEST

that switching systems are smaller, assisting the test engineer in keeping the overall
test systems smaller and reducing testfloor footprints, which can directly relate
to the advantages I referred to earlier. If
you are using a modular formfactor such
as PXI, greater switching density can mean
that you don't have to purchase that additional modular chassis for instrumentation
because switching took up too many slots.
Putting more relays on a switch module
results in shorter paths on the PCB, and as
paths get shorter, the usable bandwidth
increases. Furthermore, more relays on
a module mean less external wiring is
needed. For example, to construct a 16x32
matrix using a 16x16 module as a building block, two modules are required along
with 16 external wires. But as switching
density has increased, 16x32 modules are
available, eliminating the need for external wiring. Reducing wiring length is especially crucial in RF applications where
long signal paths result in attenuation/
loss of power.
It is important to note that higher
density designs typically require that
signal-carrying traces on the PCB be
placed closer together; this accommodates the increase in relay count, which
can increase channel-channel crosstalk.
Now let's see a few applications that
benefit from a high-density switching
system.

EVALUATION ENGINEERING FEBRUARY 2020

Semiconductor test
For years, IC chips have been getting
more complex, and consequently, so
have the test systems that verify the operation of these chips. That complexity
comes at a cost-several million dollars
per tester is not out of the question. As
a result, chip manufacturers are always
looking for ways to lower their cost of
test. True, there is still a need for those
multimillion-dollar systems for complete
chip and wafer validation, but most of
these devices can be tested in simpler
ways once good manufacturing quality
has been achieved.
It turns out that many analog tests
can be set up using a very large matrix
(Figure 3), a pulse generator, and one or
more SMUs (source/measure units). Now,
I emphasize a large matrix because of the
sheer number of test points on a wafer
or pins on a device-1,000 connections
at any one time is typical today.
The testing we are talking about here
is aimed at characterization and validation of wafers and chips/dies in product
development and NPI (new product introduction). Here are some of the tests
used:
* Wafer-level test can test for shorts/
opens and capacitance.
* I DDQ testing is a method for testing
CMOS integrated circuits for the
presence of manufacturing faults.

It relies on measuring the supply
current (I DD) in the quiescent state
(when the circuit is not switching,
and inputs are held at static values). The current consumed in this
state is commonly called I DDQ for
I DD (quiescent) and hence the name.
* For chip-level as well as wafer testing, there is I-V testing for transient
charge trapping. One version of this
test is called SPCT (Single Charge
Pulse Trapping). SPCT uses a pulse
generator to do fast I-V curves to
either avoid charge trapping or measure charge trapping as a function
of a device's switching frequency.
With some modeling work, SPCT
can distinguish the initial chargetrapping centers from those created
later by voltage stresses.
One important thing to note is that in
many of these tests, a large number of
test points must be connected to ground
to provide a stable test environment. So,
it is essential that the matrix you select
should be able to close a large number
of the matrix's relays simultaneously.
The number of relays will depend on the
product you are testing.

Figure 3: Ultrahigh-density switching matrices
for semiconductor test.

Evaluation Engineering

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