Evaluation Engineering - 23

Figure 3: Hierarchical DFT allows for complete DFT sign-off at different levels of design hierarchy.

the core level. The complete, signed-off
core is then replicated automatically to
complete the chip-level DFT implementation, as shown in Figure 2.
In the example shown in Figure
3, there are three levels of hierarchy:
core (tile), block (supertile), and chip.
The core (tile) is instantiated multiple
times in the block (supertile) which is
then instantiated multiple times at the
chip level.
In a hierarchical DFT methodology,
the DFT implementation, ATPG, and
scan-test pattern verification are performed at the core level. That is, signoff is only performed once for any given
block, then that signed-off block can
be replicated to any number of instantiations at a higher level of the design.
The same process is repeated at the
block level for the interface logic and
memory. Once the chip implementation
is complete, the test patterns for core
and block are automatically remapped
to the top level by the DFT software.
This process is much faster than performing all the DFT work and sign-off
on the whole chip after all the physical
design work is finished. Not only is it
faster, but it also adds predictability to
the project's schedule because DFT is
no longer in the critical path to tapeout.
SoC design teams who adopt hierarchical DFT have seen up to 10x faster ATPG
with 2x pattern reduction and radically
accelerate bring-up, debug, and characterization of AI chips.
Hierarchical DFT also extends to postsilicon diagnosis and failure analysis. It
allows for core-level diagnosis, which significantly accelerates the process.

Benefits of IJTAG
The benefits of hierarchical DFT are amplified when the chip also uses the IJTAG
(IEEE 1687) standard for IP integration
and test. IJTAG provides an amazing level
of flexibility and automation for on-chip
instruments. Any DFT software solution for AI chips should include IJTAG
automation as part of the hierarchical
DFT methodology. IJTAG enables two
important aspects of hierarchical DFT:
1) hierarchical verification of the IJTAG
infrastructure and 2) remapping corelevel BIST and test setup IJTAG patterns
to the top level.
For hierarchical verification, the IJTAG
network inserted at the core level is verified first at that level then again with the
IJTAG network of each higher level. When
multiple instantiations of the core are replicated at the next-higher level, the IJTAG
network from the cores is integrated and
verified automatically at that higher level.
This hierarchical IJTAG network verification ensures that errors are discovered
early in the design flow, avoiding any impact on the design schedule.
For IJTAG pattern remapping, the test
setup patterns for scan testing such as
scan-modes, low-power configuration,
etc., and BIST patterns are generated
and validated at the core level. The corelevel IJTAG patterns are automatically remapped to the chip level, which is much
faster than generating IJTAG patterns for
the entire chip from the top level.

Hierarchical DFT with core grouping
DFT implemented at the core level incurs
an area-usage penalty because the DFT
logic-like isolation wrappers, compression

logic, memory BIST controllers are duplicated in each core. However, if DFT is
implemented at the chip level, it would
result in longer ATPG runtime, large
memory requirement to load the entire
design, layout challenges when routing scan chains through all cores to the
compression engine, and test power constraints as all scan chains are active at
the same time.
AI chips need that "Goldilocks" implementation, depicted as the middle
illustration in Figure 4, which groups
multiple cores together for DFT. All the
DFT logic is inserted and signed-off at the
core group level. The DFT engineer decides how many cores to group based on
the power, test pins, test time, and layout
constraints of the design.

Other time-saving DFT techniques
Hierarchical DFT supports some key DFT
techniques that help designers further cut
DFT and test time, including:
* Broadcast the same test data to all
the identical cores with channel
broadcasting
* Share a single memory BIST controller between multiple memories
in multiple cores
* Test more cores together without increasing the test power by using an
embedded test compression (EDT)
low-power controller
When an entire chip consists of identical copies of core groups, each core group
requires the exact same test data. Channel
broadcasting is a technique to broadcast
the same test data to all the identical
core groups. This helps reduce both the
JULY 2019 EVALUATIONENGINEERING.COM

http://www.EVALUATIONENGINEERING.COM

Evaluation Engineering

Table of Contents for the Digital Edition of Evaluation Engineering