Evaluation Engineering - 25

well. Other sites, however, should not be affected. The failing
site should be reset, appropriately binning the failed device and
available to test the next device.

Key thermal protection elements in an ATE solution
There are two mechanisms that should be specified in an ATE
solution to ensure proper response to any thermal issues involved
in testing an AI device.

* After 10ms, switch VSM-Force to the VS Alt voltage level
(set to 1.1v)
* After 10ms, simulate the event
* After 10ms, switch back to the main voltage level
* After 10ms, gate off the VSM
The reason to switch to VS Alt was solely to provide a visible
marker on the voltage trace. The red trace is with automatic
shut-off trigger and the green trace is without this trigger.

The over-current alarm system
The first level of protection rests in the current clamp architecture of the ATE system. To enable fast charging of the bulk
capacitance, a dual-level clamping system allows for a higherthan-operating current to be applied without simply allowing
full power which could damage FEH or degrade its performance
over time.
The following chart shows a typical operation, where the DIB
bypass caps are charged at the overload level limit, then the
device draws an operating current that is less than the limit
specified by the fold limit.

Teradyne

This shows that the VSM output is shut down within 500us
after the trigger. (The slope change around 200mV is due to
supply switching from driving 0V to connecting to the bleeder
resistor.) Triggering Interface Monitor also triggered an alarm
on the ATE software console. This meant:
* Alarm processing functions are automatically called
* Other supplies, instruments, and channels connected to
that site would be shut down
* Alarm actions are executed, optionally failing or binning
the site
* Site bin results are sent to the handler and the data log
once all sites complete testing

Conclusion
Teradyne

After this point, the 'Fold' limit timeout can be programmed
from microseconds to seconds. If the current draw exceeds the
limit for the programmed time, the appropriate alarm action
will take effect (ignore, fail, bin).

The Interface Monitor shutdown mechanism
A good ATE system should feature a hardware real-time shutdown mechanism, or interface monitor. This will monitor the
voltage drop between the supply and the DIB interface on a persupply/per-site basis. If the voltage difference between the VS
output point and the corresponding sense point is greater than
the preset threshold value, an alarm for that site is triggered.
To illustrate how this real-time shutdown works, below is
the process for the Teradyne UltraFLEX ATE with VSM power
supply. To begin the test, a one-volt signal was applied on
the UltraFLEX tester. A pattern was run that executes the
following:
* Trigger the DC voltage input to start monitoring voltage
at the VSM power supply output

Just like CPUs before them, AI chips have a dark silicon and
thermal issues for test. However, at 7nm, those issues are unprecedented in the latest AI chips. The important ATE features
for avoiding thermal damage during ATE testing include the
overcurrent alarm system, which can warn of a thermal issue,
and the Interface Monitor that is a real-time supply shutdown
mechanism that offers fast response to a device thermal issue.
AI chip designers should evaluate their ATE solutions to ensure
that ideal thermal protection systems are in place.
Carl Peach has been with Teradyne for more than
30 years in a variety of roles supporting applications
in the linear, power, mixed-signal, digital, DSP, high
speed serial, microwave, and production integration
areas. Peach is currently an engineer in the Teradyne's
Factory Applications group.
Yi Zhang is a product manager in the Semi Test Division
at Teradyne, where he manages the computing and
communications product line. Zhang has been with
Teradyne for four years, and his current focus is the
artificial intelligence semiconductor market.
JUNE 2019 EVALUATIONENGINEERING.COM

http://www.EVALUATIONENGINEERING.COM

Evaluation Engineering

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