Evaulation_Engineering_March_2020 - 17

and setpoint verification. Specific products include the SD49
cryogenically cooled thermal platform.
Booher cited a key trend. "Everybody needs to get more with
less (time) in our competitive economy," he said. "Thermal
platforms let techs perform efficient and verifiable testing,
completed in less time, resulting in more reliable products."
Customers need speed as well as verifiable reports delivered,
he emphasized.

Electrical measurements
According to Ron Wilcox, senior director of power test engineering at Analog Devices Inc., "Twenty-five years ago, I did not
think one would be concerned with microvolts and picoamps
in power semiconductor test, but we now find ourselves measuring just those, and often in the face of challenges like > 100
VCM or in noisy environments."
He continued, "A big trend continues to be achieving higher
power density-the ability to deliver more power from a smaller
package. This continues to drive package evolution to manage
thermal and current density issues to get the power to the load."
Wilcox added, "Power semiconductor test [presents] myriad
challenges involving ever-increasing accuracies in voltage, current, and time measurements, with headwinds of higher currents, faster edges, and greater risk associated with controlling
high-energy events. Increasing digital content for control and
metrology of power semiconductors requires advanced mixedsignal test capabilities, and subnanosecond events require RF
techniques in the hardware design of test circuits. Almost every
specialized test discipline is necessary to properly test modern
power products. Add the element of danger, and one needs the
Harrison Ford of test engineers!"
Wilcox continued, "The ability to change loop response in
'VIs' or 'SMUs' helps decrease test time and prevent possible
DUT damage. Clean transitions during mode and range changes
is also paramount to preventing 'walking-wounded' devices
being generated by test, and possibly shipped to customers."
Focused Test Inc. has recently introduced several offerings
for power-semiconductor test, including a dynamic R DS(ON)
test station for the FTI-1000 test system. It performs dynamic
R DS(ON) (also known as current collapse) tests on GaN HEMTs1
with a measurement delay time of < 1 ms.
The company also introduced an inductive switching test
station for the FTI-1000 test system; it performs reverse-bias
safe operating area (RBSOA), EON/EOFF (energy loss), and other
switching tests on GaN and SiC discrete devices.
Also for the FTI-1000, the company debuted a multidie test
option for wafer-sort/circuit-probe (CP) testing of MOSFET
wafers, supporting up to 16 die in parallel, including adjacent
die test capability. It performs DC and unclamped inductive
switching (UIS) tests to 1,000 V, 100 A.
The company also supports high-voltage SiC transistor test
with a DC power source to 5 kV and UIS avalanche voltage >
3 kV, and it offers a gate-charge (QG) calibration technique for
power transistors with QG < 1 nC. The company will be highlighting these capabilities at APEC.
MARCH 2020 EVALUATIONENGINEERING.COM

http://www.EVALUATIONENGINEERING.COM

Evaulation_Engineering_March_2020

Table of Contents for the Digital Edition of Evaulation_Engineering_March_2020