JED - February 2017 - 32

A Sampling of Analog-to-Digital
Converters and ADC Boards
By Ollie Holt

T

The Journal of Electronic Defense | February 2017

32

his JED survey reviews analog-to-digital converter (ADC) components and ADC boards.
ADC components can be configured into an
EW signal acquisition module (or ADC board)
that meets the users requirements or a complete signal acquisition module can be purchased with a set of common requirements that could be
used by many different EW Systems.
Originally, EW receivers were analog devices that
through amplification and filtering measured the amplitude, frequency and time of arrival of a pulse. As radar
systems became more complex and added modulations,
like frequency and phase coding, EW and SIGINT receiver
systems required more fidelity to measure all the different radar signal parameters and to determine the best
countering technique. During the same time as radars
and EW systems were evolving, computers were getting
smaller and faster, Field Programmable Logic Arrays (FPGAs) were becoming more affordable, much easier to work
with, and the gate capacity was growing from thousands
to 10s and 100s of millions. Similarly, the analog-to-digital and digital-to-analog technology was getting much
faster and able to operate with much higher bandwidths
then the original ADC and DAC technology that was used
in simple control systems. Most of the ADC performance
growth was originally driven by the test equipment (oscilloscope and spectrum analyzer) developers trying to
fill the need of building equipment to aid in the development of higher fidelity test equipment. The EW community had similar needs to detect and measure the RF
spectrum with better fidelity to develop effective countermeasures. This need was met by incorporating ADCs
and signal processing techniques into the EW system.
What are ADCs? An DC is a device that converts an
analog value into a digital value. If the signal is a timevariant continuous signal and the ADC is set to sample
at a periodic rate, the result is a set of digitally sampled
values that represent the signals' amplitude at each
of the sample times. These periodically sampled digital values can than be signal processed using Fourier
transforms or other analytical methods to obtain useful
signal information.
At first, EW designers designed and built their own
unique signal acquisition modules to their own specifications. But as the desire/need for these modules increased, some of the usual suppliers of common 6U and
3U modules saw the market need and started providing modules with multiple ADC, DAC and FPGA compo-

nents that could easily be configured for use by the EW,
communications and radar developers. Today, there is
a large variety of these common modules in different
standard formats that can be configured easily into EW
systems.

THE SURVEY
The survey is split into two tables. The first table
covers ADCs and the second features ADC boards or
modules.
The number of bits of resolution and effective number of bits (ENOB) are not the same. An eight-bit device quantizes the input into 256 unique steps, where
a 12-bit device would quantize the same input into
4,096 unique steps. The greater number of bits provides
improvement in Spur Free Dynamic Range (SFDR). The
ENOB defines the number of bits that actually contain
useful information. The reason the ENOB figure does
not equal the actual number of bits is because analogto-digital performance is degraded by noise distortion.
ENOB can be approximated using the theoretical Signalto-Noise (SNR) of the A/D and the following equation;
ENOB = (SNR-1.76dB)/6.02.
So what is the advantage of more bits if the ENOB
for an 8-bit ADC and the ENOB for a 10-bit ADC are
both around 7.5? The advantage is that the 10-bit device probably will not need dithering and it will usually have a better SFDR. Dither is the addition of noise
into the input of the ADC to make the Least Significant
Bit (LSB) of the A/D toggle. It may sound funny, but
adding enough noise to keep the LSB toggling actually
improves device performance. An ADC with two or three
more bits of resolution than the ENOB does not need
external dithering since the quantization level will be
randomized by its internal noise.
The sample rate defines the maximum rate at which
the A/D can be operated without distortion in the measurements. It can be operated at slower clock rates but
the vendor does not support faster rates. An item not
listed in the survey but very important to the fidelity
of the analog-to-digital measurements is the sampling
clock performance. Most modules will support locking
to an external clock and provide some on module clock
filtering. As the sampling speeds get faster clock jitter
needs to be keep very low or the fidelity of the samples
will be impacted.
Next month, we will look at benchtop and field-deployable spectrum analyzers.



JED - February 2017

Table of Contents for the Digital Edition of JED - February 2017

The View From Here
Conferences Calendar
Courses Calendar
From the President
The Monitor
World Report
Asia-Pacific SIGINT Programs
Technology Survey: Analog-to-Digital Converters
Operator 101
EW 101
AOC News
Index of Advertisers
JED Quick LookThe
JED - February 2017 - cover1
JED - February 2017 - cover2
JED - February 2017 - 3
JED - February 2017 - 4
JED - February 2017 - 5
JED - February 2017 - The View From Here
JED - February 2017 - 7
JED - February 2017 - Conferences Calendar
JED - February 2017 - 9
JED - February 2017 - Courses Calendar
JED - February 2017 - 11
JED - February 2017 - From the President
JED - February 2017 - 13
JED - February 2017 - 14
JED - February 2017 - The Monitor
JED - February 2017 - insert1
JED - February 2017 - insert2
JED - February 2017 - 16
JED - February 2017 - 17
JED - February 2017 - 18
JED - February 2017 - 19
JED - February 2017 - 20
JED - February 2017 - 21
JED - February 2017 - World Report
JED - February 2017 - 23
JED - February 2017 - Asia-Pacific SIGINT Programs
JED - February 2017 - 25
JED - February 2017 - 26
JED - February 2017 - 27
JED - February 2017 - 28
JED - February 2017 - 29
JED - February 2017 - 30
JED - February 2017 - 31
JED - February 2017 - Technology Survey: Analog-to-Digital Converters
JED - February 2017 - 33
JED - February 2017 - 34
JED - February 2017 - 35
JED - February 2017 - 36
JED - February 2017 - 37
JED - February 2017 - 38
JED - February 2017 - 39
JED - February 2017 - 40
JED - February 2017 - Operator 101
JED - February 2017 - 42
JED - February 2017 - 43
JED - February 2017 - EW 101
JED - February 2017 - 45
JED - February 2017 - AOC News
JED - February 2017 - 47
JED - February 2017 - 48
JED - February 2017 - Index of Advertisers
JED - February 2017 - JED Quick LookThe
JED - February 2017 - cover3
JED - February 2017 - cover4
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