IEEE Awards Booklet - 2009 - 9

I E E E

M E D A L S

2009 IEEE
Jun-Ichi Nishizawa Medal

2009 IEEE
Richard W. Hamming Medal

Sponsored by The Federation of Electric
Power Companies, Japan and the Semiconductor
Research Foundation

Sponsored by QUALCOMM, Inc.

Peter Franaszek

Chenming Calvin Hu

For pioneering contributions to the theory and practice
of run-length constrained channel coding for magnetic
and optical storage

For technical contributions to MOS device reliability,
scaling of CMOS and compact device modeling

Known for developing codes that not only pushed the theoretical limits but were also practical enough to be implemented in
current technology, Peter Franaszek set the direction for modern
constrained coding in digital recording and communication
systems. His pioneering work on fundamental aspects of constrained codes, and algorithms for their construction, served as
the basis for key components in the proliferation of hard disk
drives, compact discs and DVDs. Specific codes he developed
have been used extensively in commercial data storage and
transmission products. Dr. Franaszek was the first to develop
practical methods for the construction of run-length limited
(RLL) codes, which ensure that the boundary lengths between
bits of data are neither too short nor too long to be detected,
resulting in maximal storage density. His (2,7) RLL code found
widespread application in magnetic and optical recording in the
1980s. More recently, Dr. Franaszek, along with Albert Widmer,
designed the (8B/10B) D.C. balanced code used, for example, in
Gigabit Ethernet and Fiber Channel systems.

Chenming Calvin Hu's seminal work on MOS reliability and
device modeling has had enormous impact on the continued
scaling of electronic devices, enabling smaller yet more functional and higher-performance integrated circuits. Dr. Hu's
work has addressed reliability and scaling issues with models
and simulation tools that are critical to current predictive capabilities in the semiconductor industry. During the 1980s, Dr. Hu
developed models capable of predicting circuit failures caused
by hot electron effects, oxide breakdown and wearout, metal
interconnect failure and the effects of external ionizing
radiation. This led to the development of highly reliable integrated circuits. Dr. Hu led the team that created the FinFET, a
promising MOSFET with a multiple-gate structure that will
allow much smaller transistors to be built and has already
enabled several corporations and universities to set records for
designing the smallest transistor.
Dr. Hu also contributed to the creation of the Berkley ShortChannel IGFET Model (BSIM) series of compact models, which
most major chip manufacturers have made their preferred
choice for circuit simulation. The research on transistor size
reduction by Dr. Hu led to innovations such as variable threshold
transistors, low-power flash memory cells, ultra-thin-body
devices and multiple-gate structures.

Dr. Franaszek's research interests have more generally included
a variety of analytical issues in digital systems. His contributions
include those to I/O architectures, switching networks, disk defragmentation algorithms, concurrency control techniques,
operating system schedulers and compression algorithms and
architectures for systems with memory compression. An IEEE
Fellow, he was the recipient of the 1989 IEEE Emanuel R. Piore
Award and the 2002 ACM Paris Kanellakis Theory and Practice
Award. Dr. Franaszek is currently a research staff member
emeritus at the IBM T.J. Watson Research Center.

An IEEE Fellow, Dr. Hu has co-authored three books, 800
research papers and supervised 60 doctoral students in the
field of semiconductor technology. He served as TSMC's Chief
Technology Officer from 2001-2004 and is currently the TSMC
Distinguished Professor of Microelectronics at the University of
California, Berkeley.

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Table of Contents for the Digital Edition of IEEE Awards Booklet - 2009

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